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general description the max16046a/max16048a eeprom-configurable sys- tem managers monitor, sequence, track, and margin mul- tiple system voltages. the max16046a manages up to twelve system voltages simultaneously, and the max16048a manages up to eight supply voltages. these devices integrate an analog-to-digital converter (adc) for monitoring supply voltages, digital-to-analog converters (dac) for adjusting supply voltages, and configurable out- puts for sequencing and tracking supplies (during power- up and power-down). nonvolatile eeprom registers are configurable for storing upper and lower voltage limits, setting timing and sequencing requirements, and for storing critical fault data for readback following failures. an internal 1% accurate 10-bit adc measures each input and compares the result to one upper, one lower, and one selectable upper or lower limit. a fault signal asserts when a monitored voltage falls outside the set limits. up to three independent fault output signals are configurable to assert under various fault conditions. the integrated sequencer/tracker allows precise control over the power-up and power-down order of up to twelve (max16046a) or up to eight (max16048a) power sup- plies. four channels (en_out1Cen_out4) support closed-loop tracking using external series mosfets. six outputs (en_out1Cen_out6) are configurable with charge-pump outputs to directly drive mosfets without closed-loop tracking. the max16046a/max16048a include twelve/eight inte- grated 8-bit dac outputs for margining power supplies when connected to the trim input of a point-of-load (pol) module. the max16046a/max16048a include six programmable general-purpose inputs/outputs (gpios). gpios are eeprom configurable as dedicated fault outputs, as a watchdog input or output (wdi/wdo), as a manual reset ( mr ), or as margin control inputs. the max16046a/max16048a feature two methods of fault management for recording information during sys- tem shutdown events. the fault logger records a failure in the internal eeprom and sets a lock bit protecting the stored fault data from accidental erasure. an i 2 c/smbus?-compatible or a jtag serial interface configures the max16046a/max16048a. these devices are offered in a 56-pin, 8mm x 8mm tqfn package or a 64-pin, 10mm x 10mm tqfp package and are fully speci- fied from -40c to +125c. features operate from 3v to 14v 1% accurate 10-bit adc monitors 12/8 inputs 12/8 monitored inputs with 1 overvoltage/ 1 undervoltage/1 selectable limit 12/8 8-bit dac outputs for margining or voltage adjustments nonvolatile fault event logger power-up and power-down sequencing capability 12/8 outputs for sequencing/power-good indicators closed-loop tracking for up to four channels two programmable fault outputs and one reset output six general-purpose input/outputs configurable as: dedicated fault output watchdog timer function manual reset margin enable input i 2 c/smbus-compatible and jtag interface eeprom-configurable time delays, thresholds, and dac outputs 100 bytes of internal user eeprom -40? to +125? operating temperature range applications servers workstations storage systems networking/telecom max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ________________________________________________________________ maxim integrated products 1 ordering information part temp range pin-package max16046a cb+ -40c to +125c 64 tqfp-ep* MAX16046ATN+ -40c to +125c 56 tqfn-ep* max16048a cb+ -40c to +125c 64 tqfp-ep* max16048atn+ -40c to +125c 56 tqfn-ep* 19-5251; rev 1; 9/10 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. + denotes a lead(pb)-free/rohs-compliant package. * ep = exposed pad. evaluation kit available smbus is a trademark of intel corp.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 2 _______________________________________________________________________________________ dacout1 dacout2? dacout11 dacout12 mon1 mon2?mon11 mon12 v supply v cc 10 f v cc +3.3v gnd a0 c scl sda reset fault int reset int i/o wdi wdo dbp en_out1 en_out1? en_out11 en_out12 en max16046a gnd out fb in dc-dc en gnd out fb in dc-dc en gnd out fb in dc-dc en 1 f abp 1 f typical operating circuit selector guide part voltage-detector inputs dac outputs general-purpose inputs/outputs sequencing outputs max16046a 12 12 6 12 max16048a 8 8 6 8
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers _______________________________________________________________________________________ 3 absolute maximum ratings electrical characteristics (v cc = 3v to 14v, t a = -40c to +125c, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25c.) (note 1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc to gnd ....................-0.3v to +15v en, mon_, scl, sda, a0 ........................................-0.3v to +6v gpio_, reset (configured as open drain) to gnd.....-0.3v to +6v en_out1Cen_out6 (configured as open drain) to gnd.................................................................-0.3v to +12v en_out7Cen_out12 (configured as open drain) to gnd...................................................................-0.3v to +6v gpio_, en_out_, reset (configured as push-pull) to gnd .........-0.3v to (v dbp + 0.3v) dbp, abp to gnd .........-0.3v to the lower of 3v or (v cc + 0.3v) tck, tms, tdi.......................................................-0.3v to +3.6v tdo ..........................................................-0.3v to (v dbp + 0.3v) dacout_.................-0.3v to (v abp + 0.3v) en_out1Cen_out6 (configured as charge pump) ............-0.3v to (v mon1C6 + 6v) continuous current (all pins)............................................20ma 56-pin tqfn (derate 47.6mw/c above +70c) .......3810mw* thermal resistance ja .................................................................................21c/w jc ................................................................................0.6c/w 64-pin tqfp (derate 43.5mw/c above +70c) ....3478.3mw* thermal resistance ja .................................................................................23c/w jc ...................................................................................1c/w lead temperature (soldering, 10s) .................................+300c soldering temperature (reflow) .......................................+260c parameter symbol conditions min typ max units reset output asserted low 1.4 operating voltage range v cc 3 14 v undervoltage lockout v uvlo 2.85 v undervoltage-lockout hysteresis uvlo hys (note 2) 50 mv supply current i cc v cc = 14v, v en = 3.3v, no load on any output 4.8 6.5 ma dbp regulator voltage v dbp c dbp = 1f, no load on any output 2.6 2.7 2.8 v abp regulator voltage v abp c abp = 1f, no load on any dacout_ 2.78 2.88 2.96 v boot time t boot v cc > v uvlo 0.8 1.5 ms internal timing accuracy (note 3) -10 +10 % adc adc resolution 10 bits mon_ range set to 00 0.65 mon_ range set to 01 0.75 t a = -40 c to +85 c mon_ range set to 10 0.95 mon_ range set to 00 0.85 mon_ range set to 01 0.95 adc total unadjusted error (note 4) adc err t a = -40 c to +125 c mon_ range set to 10 1.15 %fsr adc integral nonlinearity adc inl 0.8 lsb adc differential nonlinearity adc dnl 0.8 lsb adc total monitoring cycle time t cycle max16046a, all channels monitored, no mon_ fault detected (note 5) 120 150 s mon1Cmon4 46 100 mon_ input impedance r in mon5Cmon12 65 140 k * as per jedec 51 standard, multilayer board (pcb).
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 4 _______________________________________________________________________________________ parameter symbol conditions min typ max units mon_ range set to 00 in r0fhCr11h 5.6 mon_ range set to 01 in r0fhCr11h 2.8 adc mon_ ranges adc rng mon_ range set to 10 in r0fhCr11h 1.4 v mon_ range set to 00 in r0fhCr11h 5.46 mon_ range set to 01 in r0fhCr11h 2.73 adc lsb step size adc lsb mon_ range set to 10 in r0fhCr11h 1.36 mv v th_en_r en voltage rising 0.525 en input-voltage threshold v th_en_f en voltage falling 0.486 0.500 0.517 v en input current i en -0.5 +0.5 a en input voltage range 0 5.5 v closed-loop tracking tracking differential voltage stop ramp v trk v ins_ > v th_pl, v ins_ < v th_pg 150 mv tracking differential voltage hysteresis 20 %v trk tracking differential fault voltage v trk_f v ins_ > v th_pl ,v ins_ < v th_pg 280 325 370 mv slew-rate register set to 00 640 800 960 slew-rate register set to 01 320 400 480 slew-rate register set to 10 150 200 250 track/sequence slew-rate rising or falling trk slew slew-rate register set to 11 70 100 115 v/s power-good register set to 00, v mon _ = 3.5v 94 95 96 power-good register set to 01, v mon _ = 3.5v 91.5 92.5 93.5 power-good register set to 10, v mon _ = 3.5v 89 90 91 ins_ power-good threshold v th_pg power-good register set to 11, v mon _ = 3.5v 86.5 87.5 88.5 %v mon_ power-good threshold hysteresis v pg_hys 0.5 %v th_p g power-low threshold v th_pl ins_ falling 125 142 160 mv power-low hysteresis v th_pl_hys 10 mv gpio_ input impedance gpio inr gpio_ configured as ins_ 75 100 145 k ins_ to gnd pulldown impedance when enabled ins rpd v ins_ = 2v 100 electrical characteristics (continued) (v cc = 3v to 14v, t a = -40c to +125c, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25c.) (note 1)
max16046a/max16048a electrical characteristics (continued) (v cc = 3v to 14v, t a = -40c to +125c, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25c.) (note 1) parameter symbol conditions min typ max units dac dac resolution 8 bits dacout_ range set to 11 0.8 dacout_ range set to 10 0.6 dac output voltage range dac rng dacout_ range set to 01 0.4 v dacout_ range set to 11 3.137 dacout_ range set to 10 2.353 dac lsb step size dacout_ range set to 01 1.568 mv t a = +25c 1.195 1.202 1.208 t a = -5c to +85c 1.190 1.215 i dacout = 50a, mid code, dacout_ range set to 11 t a = -40c to +125c 1.187 1.218 t a = +25c 0.896 0.901 0.907 t a = -5c to +85c 0.890 0.912 i dacout = 50a, mid code, dacout_ range set to 10 t a = -40c to +125c 0.888 0.915 t a = +25c 0.597 0.601 0.606 t a = -5c to +85c 0.592 0.612 dac center code absolute accuracy dac acc i dacout = 50a, mid code, dacout_ range set to 01 t a = -40c to +125c 0.590 0.615 v any range, t a = -40 c to +85 c -0.8 +0.8 gain error any range, t a = -40 c to +125 c -1.0 +1.0 % dac output sink capability dac sink sinking current, i dacoutmax = 0.5ma +8 mv dac output source capability dac source sourcing current, i dacoutmax = -0.5ma -8 mv dac output switch leakage dacout_ switch off -150 +150 na dac output capacitive load (note 5) 50 pf dac output settling time 50 s dc 60 dac power-supply rejection ratio dac psrr 100mv step in 20ns with 50pf load 40 db dac differential nonlinearity dac dnl dacout_ code from 07h to f8h, any range -0.6 +0.6 lsb dac integral nonlinearity dac inl dacout_ code from 07h to f8h, any range -0.9 +0.9 lsb 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers _______________________________________________________________________________________ 5
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 6 _______________________________________________________________________________________ max16046a/max16048a electrical characteristics (continued) (v cc = 3v to 14v, t a = -40c to +125c, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25c.) (note 1) parameter symbol conditions min typ max units outputs (en_out_, reset , gpio_) output-voltage low v ol i sink = 2ma 0.4 v output-voltage high (push-pull) i source =100a 2.4 v 1 gpio1Cgpio4, v gpio_ = 3.3v 1 output leakage (open drain) i out_lkg gpio1Cgpio4, v gpio_ = 5.0v 23 a en_out_ overdrive (charge pump) (en_out1 to en_out6 only) volts above v mon_ v ov i gate_ = 0.5a 4.6 5.1 5.6 v en_out_ pullup current (charge pump) i chg_up during power-up/power-down, v gate_ = 1v 4.5 6 a en_out_ pulldown current (charge pump) i chg_down during power-up/power-down, v gate_ = 5v 10 a inputs (a0, gpio_) logic-input low voltage v il 0.8 v logic-input high voltage v ih 2.0 v smbus interface logic-input low voltage v il input voltage falling 0.8 v logic-input high voltage v ih input voltage rising 2.0 v v cc shorted to gnd, scl/sda at 0v or 3.3v -1 +1 input leakage current -1 +1 a output-voltage low v ol i sink = 3ma 0.4 v input capacitance c in 5 pf smbus timing serial clock frequency f scl 400 khz bus free time between stop and start condition t buf 1.3 s start condition setup time t su:sta 0.6 s start condition hold time t hd:sta 0.6 s stop condition setup time t su:sto 0.6 s clock low period t low 1.3 s clock high period t high 0.6 s data setup time t su:dat 200 ns t a = -40 c to +85 c 250 output fall time t of 10pf c bus 400pf t a = -40 c to +125 c 500 ns receive 0 data hold time t hd:dat transmit 0.3 0.9 s pulse width of spike suppressed t sp 30 ns
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers _______________________________________________________________________________________ 7 electrical characteristics (continued) (v cc = 3v to 14v, t a = -40c to +125c, unless otherwise specified. typical values are at v cc = 3.3v, t a = +25c.) (note 1) parameter symbol conditions min typ max units jtag interface tdi, tms, tck logic-low input voltage v il input voltage falling 0.55 v tdi, tms, tck logic-high input voltage v ih input voltage rising 2 v tdo logic-output low voltage v ol_tdo v dbp 2.5v, i sink = 2ma 0.4 v tdo logic-output high voltage v oh_tdo v dbp 2.5v, i source = 200ma 2.4 v tdo leakage current tdo high impedance -1 +1 a tdi, tms pullup resistors r jpu pullup to v dbp 7 10 13 k input/output capacitance c i/o 5 pf jtag timing tck clock period t 1 1000 ns tck high/low time t 2, t 3 50 500 ns tck to tms, tdi setup time t 4 15 ns tck to tms, tdi hold time t 5 15 ns tck to tdo delay t 6 500 ns tck to tdo high-impedance delay t 7 500 ns eeprom timing eeprom byte write cycle time t wr (note 6) 16 20 ms note 1: specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at t a = +25c and t a = +125c. specifications at t a = -40c are guaranteed by design. note 2: v uvlo is the minimum voltage on v cc to ensure the device is eeprom configured. note 3: applies to reset , fault, delay, and watchdog timeouts. note 4: total unadjusted error is a combination of gain, offset, and quantization error. note 5: guaranteed by design. note 6: an additional cycle is required when writing to configuration memory for the first time.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 8 _______________________________________________________________________________________ stop condition repeated start condition start condition t high t low t r t f t su:dat t su:sta t su:sto t hd:sta t buf t hd:sta t hd:dat scl sda start condition figure 1. i 2 c/smbus timing diagram tck t 1 t 2 t 3 t 4 t 5 t 6 t 7 tdi, tms tdo figure 2. jtag timing diagram
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers _______________________________________________________________________________________ 9 v cc supply current vs. v cc supply voltage max16046a toc01 v cc (v) i cc (ma) 13 12 1 2 3 5 6 7 8 9 10 4 11 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 0 014 t a = +85c t a = -40c t a = +125c t a = +25c normalized mon_ threshold vs. temperature max16046a toc02 temperature (c) normalized mon_ threshold 115 95 55 75 -5 15 35 -25 0.992 0.994 0.996 0.998 1.000 1.002 1.004 1.006 1.008 1.010 0.990 -45 135 2.8v range, half-scale primary undervoltage normalized en threshold vs. temperature max16046a toc03 temperature (c) normalized en threshold 115 95 55 75 -5 15 35 -25 0.93 0.94 0.95 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 0.92 -45 135 rising falling transient duration vs. threshold overdrive (en) max16046a toc04 en overdrive (mv) transient duration ( s) 10 20 40 60 80 100 120 140 160 0 1 100 max16046a toc05 temperature (c) normalized reset timeout 115 95 -25 -5 15 55 35 75 0.985 0.990 0.995 1.000 1.005 1.010 1.015 1.020 0.980 -45 135 normalized reset timeout period vs. temperature minimum transient duration vs. mon_ puv threshold overdrive max16046a toc06 threshold overdrive (mv) transient duration (s) 835 670 505 340 175 50 100 150 200 250 0 10 1000 deglitch = 2 deglitch = 4 deglitch = 8 deglitch = 16 output-voltage low vs. sink current max16046a toc07 sink current (ma) output-voltage low (v) 5 4 1 2 3 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0 06 en_out_ gpio_ typical operating characteristics (v cc = 3.3v, t a = +25c, unless otherwise noted.)
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 10 ______________________________________________________________________________________ output-voltage high vs. source current (charge-pump output) max16046a toc08 source current ( a) output-voltage high (v) 6 5 4 3 2 1 1 2 3 4 5 6 0 07 output-voltage high vs. source current (push-pull output) max16046a toc09 source current ( a) output-voltage high (v) 300 200 100 2.45 2.50 2.55 2.60 2.65 2.70 2.40 0 400 adc accuracy vs. temperature max16046a toc10 temperature (c) total unadjusted error (%) 115 95 55 75 -5 15 35 -25 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 -45 135 5.6v range, input = 2.5v fet turn-on with charge pump max16046a toc11 20ms/div v en_out_ 10v/div v source 2v/div i drain 1a/div 0v 0v 0v tracking mode max16046a toc12 20ms/div 1v/div 0v ins4 ins3 ins2 ins1 tracking mode with fast shutdown max16046a toc13 20ms/div 1v/div 0v ins4 ins3 ins2 ins1 sequencing mode max16046a toc14 40ms/div 1v/div 0v ins4 ins3 ins2 ins1 typical operating characteristics (continued) (v cc = 3.3v, t a = +25c, unless otherwise noted.)
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 11 mixed mode max16046a toc15 20ms/div 1v/div 0v ins4 ins3 ins2 ins1 dacout_ voltage vs. temperature max16046a toc16 temperature (c) dacout_ voltage (v) 115 95 55 75 -5 15 35 -25 1.12 1.14 1.16 1.18 1.20 1.22 1.24 1.26 1.28 1.30 1.10 -45 135 0.8v to 1.6v range, half scale adc dnl max16046a toc17 input voltage (digital code) adc dnl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 adc inl max16046a toc18 input voltage (digital code) adc inl (lsb) 896 768 512 640 256 384 128 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 -1.0 0 1024 internal timing accuracy vs. temperature max16046a toc19 temperature (c) normalized slot delay 115 95 55 75 -5 15 35 -25 0.96 0.97 0.98 0.99 1.00 1.01 1.02 1.03 1.04 1.05 0.95 -45 135 typical operating characteristics (continued) (v cc = 3.3v, t a = +25c, unless otherwise noted.)
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 12 ______________________________________________________________________________________ pin descriptions pin thin qfn max16046a max16048a name function 1C8 1C8 mon1C mon8 adc monitored voltage inputs. set adc input range for each mon_ through configuration registers. measured values are written to adc registers and can be read back through the i 2 c or jtag interface. 9C12 mon9C mon12 adc monitored voltage inputs. set adc input range through configuration registers. measured values are written to adc registers and can be read back through the i 2 c or jtag interface. 9C12, 33C36, 53C56 n.c. no connection. must be left unconnected. 13 13 reset configurable reset output 14 14 a0 four-state smbus address. address sampled upon por. connect a0 to ground, dbp, scl, or sda to program an individual address when connecting multiple devices. see the i 2 c/smbus-compatible serial interface section. 15 15 scl smbus serial clock input 16 16 sda smbus serial data open-drain input/output 17 17 tms jtag test mode select 18 18 tdi jtag test data in 19 19 tck jtag test clock 20 20 tdo jtag test data out 21, 40 21, 40 gnd ground. connect all gnd connections together. 22 22 gpio6 23 23 gpio5 general-purpose input/output. gpio6 and gpio5 are configurable as open-drain or push-pull outputs, dedicated fault outputs, or for watchdog functionality. gpio5 is configurable as a watchdog input (wdi). gpio6 is configurable as a watchdog output (wdo). these inputs/outputs are also configurable for margining. use the eeprom to configure gpio5 and gpio6. see the general-purpose inputs/outputs section. 24 24 en analog enable input. apply a voltage greater than the 0.525v (typ) threshold to enable all outputs. the power-down sequence is triggered when en falls below 0.5v (typ) and all outputs are deasserted. 25C32 25C32 dacout1C dacout8 dac outputs. dacout1Cdacout8 are the outputs of an internal 8-bit dac. set dacout1Cdacout8 ranges through configuration registers. connect a dacout_ to an external dc-dc converter for margining. leave dacout_ outputs unconnected, if unused. 33C36 dacout9C dacout12 dac outputs. dacout9Cdacout12 are the outputs of an internal 8-bit dac. set dacout9Cdacout12 ranges through configuration registers. connect a dacout_ to an external dc-dc converter for margining. leave dacout_ outputs unconnected, if unused.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 13 pin descriptions (continued) pin thin qfn max16046a max16048a name function 37 37 abp internal analog voltage bypass. bypass abp to gnd with a 1f ceramic capacitor. abp powers the internal circuitry of the max16046a/max16048a. do not use abp to power any external circuitry. 38 38 v cc power-supply input. bypass v cc to gnd with a 10f ceramic capacitor. 39 39 dbp internal digital voltage bypass. bypass dbp to gnd with a 1f ceramic capacitor. dbp supplies power to the eeprom memory, to the internal logic circuitry, and to the internal charge pumps when the programmable outputs are configured as charge pumps. all push-pull outputs are referenced to dbp. do not use dbp to power any external circuitry. 41 41 gpio1 general-purpose input/output 1. configure gpio1 as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open- drain/push-pull output port. use the eeprom to configure gpio1. see the general- purpose inputs/outputs section. 42 42 gpio2 general-purpose input/output 2. gpio2 is configurable as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/push-pull output port. gpio2 is also configurable as a dedicated marginup input. use the eeprom to configure gpio2. see the general-purpose inputs/outputs section. 43 43 gpio3 general-purpose input/output 3. gpio3 is configurable as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/push-pull output port. gpio3 is also configurable as a dedicated margindn input. use the eeprom to configure gpio3. see the general-purpose inputs/outputs section. 44 44 gpio4 general-purpose input/output 4. gpio4 is configurable as a logic input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/push-pull output port. gpio4 is also configurable as an active-low manual reset, mr . use the eeprom to configure gpio4. see the general-purpose inputs/outputs section. 45C50 45C50 en_out1C en_out6 output. en_out1Cen_out6 are configurable with active-high/active-low logic and with an open-drain or push-pull configuration. program the eeprom to configure en_out1Cen_out6 as a charge-pump output 5v greater than the monitored input voltage (v mon_ + 5v). en_out1Cen_out4 can also be used for closed-loop tracking. 51, 52 51, 52 en_out7C en_out8 output. configure en_out_ with active-low/active-high logic and with an open- drain or push-pull configuration. 53C56 en_out9C en_out12 output. configure en_out_ with active-low/active-high logic and with an open- drain or push-pull configuration. ep exposed pad. internally connected to gnd. connect to gnd. ep also functions as a heatsink to maximize thermal dissipation. do not use as the main ground connection.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 14 ______________________________________________________________________________________ pin descriptions (continued) pin tqfp max16046a max16048a name function 1C7, 10 1C7, 10 mon1C mon8 adc monitored voltage inputs. set adc input range for each in_ through configuration registers. measured values are written to adc registers and can be read back through the i 2 c or jtag interface. 11C14 mon9C mon12 adc monitored voltage inputs. set adc input range through configuration registers. measured values are written to adc registers and can be read back through the i 2 c or jtag interface. 8, 9, 15, 25, 33, 48, 49, 64 8, 9, 11C15, 25, 33, 38C 41, 48, 49, 60C64 n.c. no connection. must leave unconnected. 16 16 reset configurable reset output 17 17 a0 four-state smbus address. address sampled upon por. connect a0 to ground, dbp, scl, or sda to program an individual address when connecting multiple devices. see the i 2 c/smbus-compatible serial interface section. 18 18 scl smbus serial clock input 19 19 sda smbus serial data open-drain input/output 20 20 tms jtag test mode select 21 21 tdi jtag test data in 22 22 tck jtag test clock 23 23 tdo jtag test data out 24, 45 24, 45 gnd ground 26, 27 26, 27 gpio6, gpio5 general-purpose input/output. gpio6 and gpio5 are configurable as open-drain or push-pull outputs, dedicated fault outputs, or for watchdog functionality. gpio5 is configurable as a watchdog input (wdi). gpio6 is configurable as a watchdog output (wdo). these inputs/outputs are also configurable for margining. use the eeprom to gpio5 and gpio6. see the general-purpose inputs/outputs section. 28 28 en analog enable input. apply a voltage greater than the 0.525v (typ) threshold to enable all outputs. power-down sequence triggered when en falls below 0.5v (typ) and all outputs are deasserted. 29C32, 34C37 29C32, 34C37 dacout1C dacout8 dac outputs. dacout1Cdacout8 are the outputs of an internal 8-bit dac. set dacout_ ranges through configuration registers. connect a dacout_ to an external dc-dc converter for margining. leave dacout_ outputs unconnected, if unused. 38C41 dacout9C dacout12 dac outputs. dacout9Cdacout12 are the outputs of an internal 8-bit dac. set dacout_ ranges range through configuration registers. connect a dacout_ to an external dc-dc converter for margining. leave dacout_ outputs unconnected, if unused.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 15 pin descriptions (continued) pin tqfp max16046a max16048a name function 42 42 abp internal analog voltage regulator output. bypass abp to gnd with a 1f ceramic capacitor. abp powers the internal circuitry of the max16046a/max16048a and supplies power to the internal charge pumps when the programmable outputs are configured as charge pumps. do not use abp to power any external circuitry. 43 43 v cc power-supply input. bypass v cc to gnd with a 10f ceramic capacitor. 44 44 dbp internal digital voltage regulator output. bypass dbp to gnd with a 1f ceramic capacitor. dbp supplies power to the eeprom memory and the internal logic circuitry. all push-pull outputs are referenced to dbp. do not use dbp to power any external circuitry. 46 46 gpio1 general-purpose input/output 1. configure gpio1 as a ttl input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open- drain/push-pull output port. use the eeprom to configure gpio1. see the general- purpose inputs/outputs section. 47 47 gpio2 general-purpose input/output 2. gpio2 is configurable as a ttl input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/push-pull output port. gpio2 is also configurable as a dedicated marginup input. use the eeprom to configure gpio2. see the general-purpose inputs/outputs section. 50 50 gpio3 general-purpose input/output 3. gpio3 is configurable as a ttl input, a return sense line for closed-loop tracking, an open-drain/push-pull fault output, or an open-drain/push-pull output port. gpio3 is also configurable as a dedicated margindn input. use the eeprom to configure gpio3. see the general-purpose inputs/outputs section. 51 51 gpio4 general-purpose input/output 4. gpio4 is configurable as a ttl input, a return sense line for closed loop tracking, an open-drain/push-pull fault output, or an open-drain/push-pull output port. gpio4 is also configurable as an active-low manual reset, mr . use the eeprom to configure gpio4. see the general-purpose inputs/outputs section. 52C57 52C57 en_out1C en_out6 output. en_out1Cen_out6 are configurable with active-high/active-low logic and with open-drain or push-pull configurations. program the eeprom to configure en_out_ with a charge-pump output 5v greater than the monitored input voltage (v in_ + 5v). en_out1Cen_out4 can also be used for closed-loop tracking. 58, 59 58, 59 en_out7, en_out8 output. configure en_out_ with active-low/active-high logic and with an open- drain or push-pull configuration. 60C63 en_out9C en_out12 output. configure en_out_ with active-low/active-high logic and with an open- drain or push-pull configuration. ep exposed pad. internally connected to gnd. connect to gnd. ep also functions as a heatsink to maximize thermal dissipation. do not use as the main ground connection.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 16 ______________________________________________________________________________________ functional diagram en v th_en voltage scaling and mux 10-bit adc (sar) adc registers threshold registers digital comparators track and hold ( ) max16048a only. 8-bit dac dac registers ram registers eeprom registers logic sequencer closed-loop tracker i 2 c slave interface jtag interface mon1? mon12 (mon1? mon8) dacout1? dacout12 (dacout1? dacout8) reset fault1 fault2 mr margin watchdog timer wdi gpio control wdo gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 ins1 ins2 ins3 ins4 en_out1? en_out12 (en_out1? en_out8) en_out1? en_out4 a0 sda scl tms tck tdi tdo marginup margindn faultpu gnd v cc nonvolatile fault event logger max16046a max16048a
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 17 register summary (all registers 8-bits wide) page register description adc conversion results (registers r00h to r17h) input adc conversion results. adc writes directly to these registers during normal operation. adc input ranges (mon1Cmon12) are selected with registers r0fh to r11h. failed line flags (registers r18h to r19h) voltage fault flag bits. flags for each input signal when undervoltage or overvoltage threshold is exceeded. gpio data (registers r1ah to r1bh) gpio state data. used to read back and control the state of each gpio. extended dac enables (registers r1ch to r1dh) dac output control. controls whether dac outputs are high impedance or connected to the dac. default dac registers (registers r00h to r0bh) dac code registers. sets the output voltage of each dac output. adc range selections (registers r0fh to r11h) adc input voltage range. selects the voltage range of the monitored inputs. dac range (registers r12h to r14h) dac range registers. sets the voltage output range of each dac output. reset and fault outputs (registers r15h to r1bh) reset and fault1 C fault2 output configuration. programs the functionality of the reset , fault1 , and fault2 outputs, as well as which inputs they depend on. gpio configuration (registers r1ch to r1eh) general-purpose input/output configuration registers. gpios are configurable as a manual-reset input, a margin disable input, margin-up/margin-down control inputs, a watchdog timer input and output, logic inputs/outputs, fault-dependent outputs, or as the feedback/pulldown inputs (ins_) for closed-loop tracking. programmable output configuration (registers r1fh to r22h) programmable output configurations. selectable output configurations include: active- low or active-high, open-drain or push-pull outputs. en_out1Cen_out6 are configurable as charge-pump outputs, and en_out1Cen_out4 can be configured for closed-loop tracking. overvoltage and undervoltage thresholds (registers r23h to r46h) input overvoltage and undervoltage thresholds. adc conversion results are compared to overvoltage and undervoltage threshold values stored here. mon_ voltages exceeding threshold values trigger a fault event. fault behavior (registers r47h to r4ch) selects how the device should operate during faults. options include latch-off or autoretry after fault. the autoretry delay is selectable (r4fh). use registers r48h through r4ch to select fault conditions that trigger a critical fault event. software enable and margin (register r4dh) use register r4dh to set the software enable bit, to select early warning thresholds and undervoltage/overvoltage, to enable/disable margining, and to enable/disable the watchdog for independent/dependent mode. s eq uenci ng - m od e c onfi g ur ati on ( reg i ster s r 50h to r 5bh and r 5e h to r 63h) assign inputs and outputs for sequencing. select sequence delays (20s to 1.6s) with registers r50h through r54h. use register r54h to enable/disable the reverse sequence bit for power-down operation. watchdog functionality (register r55h) configure watchdog functionality for gpio5 and gpio6. default and eeprom dac output margin levels (registers r66h to r7dh) dac output levels depend on gpio2 and gpio3 when configured for margining functionality. set registers r66h to r71h for margin up. set registers r72h to r7dh for margin down. fault log results (registers r00h to r0eh) adc conversion results and failed-line flags at the time of a fault. these values are recorded by the fault event logger at the time of a critical fault. eeprom user eeprom (registers r9ch to rffh) user-available eeprom note: this data sheet uses a specific convention for referring to bits within a particular address location. as an example, r0fh[3:0] refers to bit 3 to bit 0 in register with address 15 decimal.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 18 ______________________________________________________________________________________ detailed description getting started the max16046a is capable of managing up to twelve system voltages simultaneously, and the max16048a can manage up to eight system voltages. after boot- up, if en is high and the software enable bit is set to 0, an internal multiplexer cycles through each input. at each multiplexer stop, the 10-bit adc converts the monitored analog voltage to a digital result and stores the result in a register. each time the multiplexer finish- es a conversion (12.45s max), internal logic circuitry compares the conversion results to the overvoltage and undervoltage thresholds stored in memory. when a conversion violates a programmed threshold, the con- version can be configured to generate a fault. logic outputs can be programmed to depend on many com- binations of faults. additionally, faults are programma- ble to trigger the nonvolatile fault logger, which writes all fault information automatically to the eeprom and write-protects the data to prevent accidental erasure. the max16046a/max16048a contain both i 2 c/smbus and jtag serial interfaces for accessing registers and eeprom. use only one interface at any given time. for more information on how to access the internal memory through these interfaces, see the i 2 c/smbus-compatible serial interface and jtag serial interface sections. registers are divided into three pages with access con- trolled by special i 2 c and jtag commands. the factory-default values at por (power-on reset) for all ram registers are 0s. por occurs when v cc reach- es the undervoltage-lockout threshold (uvlo) of 2.85v (max). at por, the device begins a boot-up sequence. during the boot-up sequence, all monitored inputs are masked from initiating faults and eeprom contents are copied to the respective register locations. during boot- up, the max16046a/max16048a are not accessible through the serial interface. the boot-up sequence can take up to 1.5ms, after which the device is ready for normal operation. reset is low during boot-up and asserts after boot-up for its programmed timeout period once all monitored channels are within their respective thresholds. during boot-up, the gpios, dacouts, and en_outs are high impedance. accessing the eeprom the max16046a/max16048a memory is divided into three separate pages. the default page, selected by default at por, contains configuration bits for all func- tions of the part. the extended page contains the adc conversion results, gpio input and output registers, and dac enable bits. finally, the eeprom page con- tains all stored configuration information as well as saved fault data and user-defined data. see the register map table for more information on the function of each register. during the boot-up sequence, the contents of the eeprom (r0fh to r7dh) are copied into the default page (r0fh to r7dh). registers r00h to r0bh of the default page contain the dac output voltage registers and are reset to 0s at por. registers r00h to r0eh of the eeprom page contain saved fault data. the jtag and i 2 c interfaces provide access to all three pages. each interface provides commands to select and deselect a particular page: ? 98h(i 2 c)/09h(jtag)switches to the extended page. switch back to the default page with 99h(i 2 c)/0ah(jtag). ? 9ah(i 2 c)/0bh(jtag)switches to the eeprom page. switch back to the default page with 9bh(i 2 c)/0ch(jtag). see the i 2 c/smbus-compatible serial interface or the jtag serial interface section. power apply 3v to 14v to v cc to power the max16046a/ max16048a. bypass v cc to ground with a 10f capaci- tor. two internal voltage regulators, abp and dbp, supply power to the analog and digital circuitry within the device. do not use abp or dbp to power external circuitry. abp is a 2.85v (typ) voltage regulator that powers the internal analog circuitry and supplies power to the dac outputs. bypass the abp output to gnd with a 1f ceramic capacitor installed as close to the device as possible. dbp is an internal 2.7v (typ) voltage regulator. eeprom and digital circuitry are powered by dbp. all push-pull outputs are referenced to dbp. dbp supplies the input voltage to the internal charge pumps when the programmable outputs are configured as charge- pump outputs. bypass the dbp output to gnd with a 1f ceramic capacitor installed as close as possible to the device.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 19 enable to initiate sequencing/tracking and enable monitoring, the voltage at en must be above 0.525v and the software enable bit in r4dh[0] must be set to 0. to power down and disable monitoring, either pull en below 0.5v or set the software enable bit to 1. see table 1 for the software enable bit configurations. connect en to abp if not used. if en is driven by exter- nal logic instead of from the center tap of a v cc -con- nected resistive divider, ensure that an active-high pulse occurs on en within 1.5ms of v cc exceeding 2.85v. if the external driving logic is in the high-imped- ance state during power-up, this pulse can be created by connecting an external pullup resistor to en if a fault condition occurs during the power-up cycle, the en_out_ outputs are powered down immediately, independent of the state of en. if operating in latch-on fault mode, toggle en or toggle the software enable bit to clear the latch condition and restart the device once the fault condition has been removed. table 1. eeprom software enable configurations register/ eeprom address bit range description 0 software enable bit 0 = enabled. en must also be high to begin sequencing. 1 = disabled (factory default) 1 margin bit 1 = margin functionality is enabled 0 = margin disabled 2 early warning selection bit 0 = early warning thresholds are undervoltage thresholds 1 = early warning thresholds are overvoltage thresholds 3 watchdog mode selection bit 0 = watchdog timer is in dependent mode 1 = watchdog timer is in independent mode 4dh [7:4] not used voltage monitoring the max16046a/max16048a feature an internal 10-bit adc that monitors the mon_ voltage inputs. an internal multiplexer cycles through each of the twelve inputs, taking 150s (typ) for a complete monitoring cycle. each acquisition takes approximately 12.45s. at each multiplexer stop, the 10-bit adc converts the analog input to a digital result and stores the result in a regis- ter. adc conversion results are stored in registers r00h to r17h in the extended page. use the i 2 c or jtag seri- al interface to read adc conversion results. see the i 2 c/smbus-compatible serial interface or the jtag serial interface section for more information on access- ing the extended page. the max16046a provides twelve inputs, mon1C mon12, for voltage monitoring. the max16048a pro- vides eight inputs, mon1Cmon8, for voltage monitor- ing. each input voltage range is programmable in registers r0fh to r11h (see table 2). when mon_ con- figuration registers are set to 11, mon_ voltages are not monitored or converted, and the multiplexer does not stop at these inputs, decreasing the total cycle time. these inputs cannot be configured to trigger fault conditions. the three programmable thresholds for each monitored voltage include an overvoltage, an undervoltage, and an early warning threshold that can be set in r4dh[2] to be either an undervoltage or overvoltage threshold. see the faults section for more information on setting over- voltage and undervoltage thresholds. all voltage thresholds are 8 bits wide. the 8 msbs of the 10-bit adc conversion result are compared to these overvolt- age and undervoltage thresholds. for any undervoltage or overvoltage condition to be monitored and any faults detected, the mon_ input must be assigned to a particular sequence order. see the sequencing section for more details on assigning mon_ inputs.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 20 ______________________________________________________________________________________ table 2. input monitor ranges and enables register/ eeprom address bit range description [1:0] mon1 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon1 is not converted or monitored [3:2] mon2 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon2 is not converted or monitored [5:4] mon3 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon3 is not converted or monitored 0fh [7:6] mon4 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon4 is not converted or monitored [1:0] mon5 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon5 is not converted or monitored [3:2] mon6 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon6 is not converted or monitored [5:4] mon7 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon7 is not converted or monitored 10h [7:6] mon8 voltage range selection: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon8 is not converted or monitored
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 21 table 2. input monitor ranges and enables (continued) register/ eeprom address bit range description [1:0] mon9 voltage range selection*: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon9 is not converted or monitored [3:2] mon10 voltage range selection*: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon10 is not converted or monitored [5:4] mon11 voltage range selection*: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon11 is not converted or monitored 11h [7:6] mon12 voltage range selection*: 00 = from 0 to 5.6v in 5.46mv steps 01 = from 0 to 2.8v in 2.73mv steps 10 = from 0 to 1.4v in 1.36mv steps 11 = mon12 is not converted or monitored * max16046a only
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 22 ______________________________________________________________________________________ the extended memory page contains the adc conver- sion result registers (see table 3). these registers are also used internally for fault threshold comparison. voltage-monitoring thresholds are compared with the 8 msbs of the conversion results. inputs that are not enabled are not converted by the adc; they contain the last value acquired before that channel was disabled. the adc conversion result registers are reset to 00h at boot-up. these registers are not reset when a reboot command is executed. table 3. adc conversion registers extended page address bit range description 00h [7:0] mon1 adc conversion result (msb) [7:6] mon1 adc conversion result (lsb) 01h [5:0] reserved 02h [7:0] mon2 adc conversion result (msb) [7:6] mon2 adc conversion result (lsb) 03h [5:0] reserved 04h [7:0] mon3 adc conversion result (msb) [7:6] mon3 adc conversion result (lsb) 05h [5:0] reserved 06h [7:0] mon4 adc conversion result (msb) [7:6] mon4 adc conversion result (lsb) 07h [5:0] reserved 08h [7:0] mon5 adc conversion result (msb) [7:6] mon5 adc conversion result (lsb) 09h [5:0] reserved 0ah [7:0] mon6 adc conversion result (msb) [7:6] mon6 adc conversion result (lsb) 0bh [5:0] reserved 0ch [7:0] mon7 adc conversion result (msb) [7:6] mon7 adc conversion result (lsb) 0dh [5:0] reserved 0eh [7:0] mon8 adc conversion result (msb) [7:6] mon8 adc conversion result (lsb) 0fh [5:0] reserved 10h [7:0] mon9 adc conversion result (msb)* [7:6] mon9 adc conversion result (lsb)* 11h [5:0] reserved 12h [7:0] mon10 adc conversion result (msb)* [7:6] mon10 adc conversion result (lsb)* 13h [5:0] reserved 14h [7:0] mon11 adc conversion result (msb)* [7:6] mon11 adc conversion result (lsb)* 15h [5:0] reserved 16h [7:0] mon12 adc conversion result (msb)* [7:6] mon12 adc conversion result (lsb)* 17h [5:0] reserved * max16046a only
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 23 general-purpose inputs/outputs gpio1Cgpio6 are programmable general-purpose inputs/outputs. gpio1Cgpio6 are configurable as a manual reset input, a margin disable input, margin- up/margin-down control inputs, a watchdog timer input and output, logic inputs/outputs, fault-dependent out- puts, or as the feedback inputs (ins_) for closed-loop tracking. when programmed as outputs, gpios are open drain or push-pull. see registers r1ch to r1eh in tables 4 and 5 for more detailed information on config- uring gpio1Cgpio6. table 4. general-purpose io configuration registers register/ eeprom address bit range description [2:0] gpio1 configuration register [5:3] gpio2 configuration register 1ch [7:6] gpio3 configuration register (lsb) [0] gpio3 configuration register (msb) [3:1] gpio4 configuration register [6:4] gpio5 configuration register 1dh [7] gpio6 configuration register (lsb) [1:0] gpio6 configuration register (msb) 1eh [7:2] reserved table 5. gpio mode selection configuration bits gpio1 gpio2 gpio3 gpio4 gpio5 gpio6 000 ins1 ins2 ins3 ins4 margin input 001 push-pull logic input/output push-pull logic input/output push-pull logic input/output push-pull logic input/output push-pull logic input/output push-pull logic input/output 010 open-drain logic input/output open-drain logic input/output open-drain logic input/ output open-drain logic input/output open-drain logic input/ output open-drain logic input/ output 011 push-pull any_fault output push-pull any_fault output push-pull any_fault output push-pull any_fault output push-pull fault1 output push-pull fault2 output 100 open-drain any_fault output open-drain any_fault output open-drain any_fault output open-drain any_fault output open-drain fault1 output open-drain fault2 output 101 logic input logic input logic input logic input logic input logic input 110 open-drain, wdo output 111 marginup input margindn input mr input wdi input open-drain, faultpu output note: the dash represents a reserved gpio configuration. do not set any gpio to these values.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 24 ______________________________________________________________________________________ voltage tracking sense (ins_) inputs gpio1Cgpio4 are configurable as feedback sense return inputs (ins_) for closed-loop tracking. connect the gate of an external n-channel mosfet to each en_out_ configured for closed-loop tracking. connect ins_ inputs to the source of the mosfets for tracking feedback. internal comparators monitor ins_ with respect to a control tracking ramp voltage for power-up/power-down and control each en_out_ voltage. under normal con- ditions each ins_ voltage tracks the ramp voltage until the power-good voltage threshold has been reached. the slew rate for the ramp voltage and the ins_ to mon_ power-good threshold are programmable. see the closed-loop tracking section. ins_ connections can also act as 100 ? pulldowns for closed-loop tracking channels or for other power sup- plies, if ins_ are connected to the outputs of the sup- plies. set the appropriate bits in r4eh[7:4] to enable pulldown functionality. see table 13. general-purpose logic inputs/outputs configure gpio1Cgpio6 to be used as general-pur- pose inputs/outputs. write values to gpios through r1ah when operating as outputs, and read values from r1bh when operating as inputs. register r1bh is read- only. see table 6 for more information on reading and writing to the gpios as logic inputs/outputs. both regis- ters r1ah and r1bh are located in the extended page and are therefore not loaded from eeprom on boot-up. table 6. gpio data-in/data-out data extended page address bit range description [0] gpio logic output data 0 = gpio1 is a logic-low output 1 = gpio1 is a logic-high output [1] 0 = gpio2 is a logic-low output 1 = gpio2 is a logic-high output [2] 0 = gpio3 is a logic-low output 1 = gpio3 is a logic-high output [3] 0 = gpio4 is a logic-low output 1 = gpio4 is a logic-high output [4] 0 = gpio5 is a logic-low output 1 = gpio5 is a logic-high output [5] 0 = gpio6 is a logic-low output 1 = gpio6 is a logic-high output 1ah [7:6] not used [0] gpio logic input data gpio1 logic-input state [1] gpio2 logic-input state [2] gpio3 logic-input state [3] gpio4 logic-input state [4] gpio5 logic-input state [5] gpio6 logic-input state 1bh [7:6] not used
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 25 any_fault outputs gpio1Cgpio4 are configurable as active-low push-pull or open-drain fault-dependent outputs. these outputs assert when any monitored input exceeds an overvolt- age, undervoltage, or early warning threshold. fault1 and fault2 gpio5 and gpio6 are configurable as dedicated fault outputs, fault1 and fault2 , respectively. fault outputs can assert on one or more overvoltage, under- voltage, or early warning conditions for selected inputs. fault1 and fault2 dependencies are set using reg- isters r15h to r18h. see table 7. if a fault output depends on more than one mon_, the fault output will assert if one or more mon_ exceeds a programmed threshold voltage. table 7. fault1 and fault2 output configuration and dependencies register/ eeprom address bit range description [0] 1 = fault1 is a digital output dependent on mon1 [1] 1 = fault1 is a digital output dependent on mon2 [2] 1 = fault1 is a digital output dependent on mon3 [3] 1 = fault1 is a digital output dependent on mon4 [4] 1 = fault1 is a digital output dependent on mon5 [5] 1 = fault1 is a digital output dependent on mon6 [6] 1 = fault1 is a digital output dependent on mon7 15h [7] 1 = fault1 is a digital output dependent on mon8 [0] 1 = fault1 is a digital output dependent on mon9* [1] 1 = fault1 is a digital output dependent on mon10* [2] 1 = fault1 is a digital output dependent on mon11* [3] 1 = fault1 is a digital output dependent on mon12* [4] 1 = fault1 is a digital output that depends on the overvoltage thresholds at the input selected by r15h and r16h[3:0] [5] 1 = fault1 is a digital output that depends on the undervoltage thresholds at the input selected by r15h and r16h[3:0] [6] 1 = fault1 is a digital output that depends on the early warning thresholds at the input selected by r15h and r16h[3:0] 16h [7] 0 = fault1 is an active-low digital output 1 = fault1 is an active-high digital output [0] 1 = fault2 is a digital output dependent on mon1 [1] 1 = fault2 is a digital output dependent on mon2 [2] 1 = fault2 is a digital output dependent on mon3 [3] 1 = fault2 is a digital output dependent on mon4 [4] 1 = fault2 is a digital output dependent on mon5 [5] 1 = fault2 is a digital output dependent on mon6 [6] 1 = fault2 is a digital output dependent on mon7 17h [7] 1 = fault2 is a digital output dependent on mon8
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 26 ______________________________________________________________________________________ fault-on power-up ( faultpu ) gpio6 indicates a fault during power-up or power- down when configured as a fault-on power-up output. under these conditions, all en_out_ voltages are pulled low and fault data is saved to nonvolatile eeprom. see the faults section. marginup and margindn configure gpio2 and gpio3 as margin-up ( marginup ) and margin-down ( margindn ) inputs, respectively, for margining functionality. pull marginup low and pull margindn high to select dacout_ voltage values set in registers r66h to r71h. pull margindn low and pull marginup high to select dacout_ values set in registers r72h to r7dh. pull both marginup and margindn high or low to select dacout_ values set in registers r00h to r0bh. see the voltage margining section for more information on set- ting dacout_ outputs for margining. margin-up and margin-down functionality is controlled by gpio2 and gpio3 when configured for margining (see table 8). when marginup or margindn are asserted, the dac output switches are automatically closed and the margin function is enabled. writing to the dac-enabled registers (r1ch and r1dh) is not required to close the dac switches. see the margin section for an explanation of the margin function. table 7. fault1 and fault2 output configuration and dependencies (continued) register/ eeprom address bit range description [0] 1 = fault2 is a digital output dependent on mon9* [1] 1 = fault2 is a digital output dependent on mon10* [2] 1 = fault2 is a digital output dependent on mon11* [3] 1 = fault2 is a digital output dependent on mon12* [4] 1 = fault2 is a digital output that depends on the overvoltage thresholds at the input selected by r17h and r18h[3:0] [5] 1 = fault2 is a digital output that depends on the undervoltage thresholds at the input selected by r17h and 18h[3:0] [6] 1 = fault2 is a digital output that depends on the early warning thresholds at the input selected by r17h and r18h[3:0] 18h [7] 0 = fault2 is an active-low digital output 1 = fault2 is an active-high digital output * max16046a only table 8. marginup and margindn function marginup (gpio2) margindn (gpio3) dacout register used dacout switch state 1 1 dacout registers r00h to r0bh depends on r1ch, r1dh* 10 margindn registers r72h to r7dh closed 01 marginup registers r66h to r71h closed 0 0 dacout registers r00h to r0bh depends on r1ch, r1dh* * note: r1ch and r1dh are located in the extended page.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 27 margin gpio6 is configurable as an active-low margin input. drive margin low before varying system voltages above or below the thresholds to avoid signaling an error. drive margin high for normal operation. when margin is pulled low or r4dh[1] is a 1, the mar- gin function is enabled. fault1 , fault2 , any_fault, and reset are latched in their current state. threshold violations will be ignored, and faults will not be logged. manual reset ( mr ) gpio4 is configurable to act as an active-low manual reset input, mr . drive mr low to assert reset . reset remains low for the selected reset timeout period after mr transitions from low to high. see the reset section for more information on selecting a reset timeout period. watchdog input (wdi) and output (wdo) set r1eh[1:0] and register r1dh[7] to 110 to configure gpio6 as wdo. set r1dh[6:4] to 111 to configure gpio5 as wdi. wdo is an open-drain active-low output. see the watchdog timer section for more information about the operation of the watchdog timer. programmable outputs (en_out1?n_out12) the max16046a includes twelve programmable out- puts, and the max16048a includes eight programma- ble outputs. these outputs are capable of connecting to either the enable (en) inputs of a dc-dc or ldo power supply or to the gates of series-pass mosfets for closed-loop tracking mode, or for charge-pump mode. selectable output configurations include: active- low or active-high, open-drain or push-pull. en_out1Cen_out4 are also configurable for closed- loop tracking, and en_out1Cen_out6 can act as charge-pump outputs with no closed-loop tracking. use the registers r1fh to r22h to configure outputs. see table 9 for detailed information on configuring en_out1Cen_out12. table 9. en_out1?n_out12 configuration register/ eeprom address bit range description [2:0] en_out1 configuration: 000 = en_out1 is an open-drain active-low output 001 = en_out1 is an open-drain active-high output 010 = en_out1 is a push-pull active-low output 011 = en_out1 is a push-pull active-high output 100 = en_out1 is used in closed-loop tracking 101 = en_out1 is configured with a charge-pump output (mon1 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved [5:3] en_out2 configuration: 000 = en_out2 is an open-drain active-low output 001 = en_out2 is an open-drain active-high output 010 = en_out2 is a push-pull active-low output 011 = en_out2 is a push-pull active-high output 100 = en_out2 is used in closed-loop tracking 101 = en_out2 is configured with a charge-pump output (mon2 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved 1fh [7:6] en_out3 configuration (lsbs): 000 = en_out3 is an open-drain active-low output 001 = en_out3 is an open-drain active-high output 010 = en_out3 is a push-pull active-low output 011 = en_out3 is a push-pull active-high output 100 = en_out3 is used in closed-loop tracking 101 = en_out3 is configured with a charge-pump output (mon3 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 28 ______________________________________________________________________________________ table 9. en_out1?n_out12 configuration (continued) register/eeprom address bit range description [0] en_out3 configuration (msb) see r1fh[7:6] [3:1] en_out4 configuration: 000 = en_out4 is an open-drain active-low output 001 = en_out4 is an open-drain active-high output 010 = en_out4 is a push-pull active-low output 011 = en_out4 is a push-pull active-high output 100 = en_out4 is used in closed-loop tracking 101 = en_out4 is configured with a charge-pump output (mon4 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved [6:4] en_out5 configuration: 000 = en_out5 is an open-drain active-low output 001 = en_out5 is an open-drain active-high output 010 = en_out5 is a push-pull active low output 011 = en_out5 is a push-pull active-high output 100 = reserved. en_out5 is not usable for closed-loop tracking. 101 = en_out5 is configured with a charge-pump output (mon5 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved 20h [7] en_out6 configuration (lsb) see r21h[1:0] [1:0] en_out6 configuration (msbs): 000 = en_out6 is an open-drain active-low output 001 = en_out6 is an open-drain active-high output 010 = en_out6 is a push-pull active-low output 011 = en_out6 is a push-pull active-high output 100 = reserved. en_out6 is not useable for closed-loop tracking. 101 = en_out6 is configured with a charge-pump output (mon6 + 5v) capable of driving an external n-channel mosfet 110 = reserved 111 = reserved [3:2] en_out7 configuration: 00 = en_out7 is an open-drain active-low output 01 = en_out7 is an open-drain active-high output 10 = en_out7 is a push-pull active-low output 11 = en_out7 is a push-pull active-high output [5:4] en_out8 configuration: 00 = en_out8 is an open-drain active-low output 01 = en_out8 is an open-drain active-high output 10 = en_out8 is a push-pull active-low output 11 = en_out8 is a push-pull active-high output 21h [7:6] en_out9 configuration*: 00 = en_out9 is an open-drain active-low output 01 = en_out9 is an open-drain active-high output 10 = en_out9 is a push-pull active-low output 11 = en_out9 is a push-pull active-high output
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 29 table 9. en_out1?n_out12 configuration (continued) register/eeprom address bit range description [1:0] en_out10 configuration*: 00 = en_out10 is an open-drain active-low output 01 = en_out10 is an open-drain active-high output 10 = en_out10 is a push-pull active-low output 11 = en_out10 is a push-pull active-high output [3:2] en_out11 configuration*: 00 = en_out11 is an open-drain active-low output 01 = en_out11 is an open-drain active-high output 10 = en_out11 is a push-pull active-low output 11 = en_out11 is a push-pull active-high output [5:4] en_out12 configuration*: 00 = en_out12 is an open-drain active-low output 01 = en_out12 is an open-drain active high output 10 = en_out12 is a push-pull active-low output 11 = en_out12 is a push-pull active-high output 22h [7:6] reserved * max16046a only charge-pump configuration en_out1Cen_out6 can act as high-voltage charge- pump outputs to drive up to six external n-channel mosfets. during sequencing, an en_out_ output configured this way drives 6a until the voltage reach- es 5v above the corresponding mon_ to fully enhance the external n-channel mosfet. for example, en_out2 will rise to 5v above mon2. see the sequencing section for more detailed information on power-supply sequencing. closed-loop tracking operation en_out1Cen_out4 can operate in closed-loop track- ing mode. when configured for closed-loop tracking, en_out1Cen_out4 are capable of driving the gates of up to four external n-channel mosfets. for closed- loop tracking, configure gpio1Cgpio4 as return-sense line inputs (ins_) to be used in conjunction with en_out1Cen_out4 and mon1Cmon4. see the closed-loop tracking section. open-drain output configuration connect an external pullup resistor from the output to an external voltage up to 6v (abs max, en_out7 to en_out12) or 12v (abs max, en_out1 to en_out6) when configured as an open-drain output. choose the pullup resistor depending on the number of devices connected to the open-drain output and the allowable current consumption. the open-drain output configura- tion allows wire-ored connection. push-pull output configuration the max16046a/max16048as programmable outputs sink 2ma and source 100a when configured as push- pull outputs. en_out_ state during power-up when v cc is ramped from 0v to the operating supply voltage, the en_out_ output is high impedance until v cc is approximately 2.4v and then en_out_ will be in its configured deasserted state. see figures 3 and 4. reset is configured as an active-low open-drain output pulled up to v cc through a 10k ? resistor for figures 3 and 4.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 30 ______________________________________________________________________________________ sequencing each en_out_ has one or more associated mon_ inputs, facilitating the voltage monitoring of multiple power supplies. to sequence a system of power sup- plies safely, the output voltage of a power supply must be good before the next power supply may turn on. connect en_out_ outputs to the enable input of an external power supply and connect mon_ inputs to the output of the power supply for voltage monitoring. more than one mon_ may be used if the power supply has multiple outputs. sequence order the max16046a/max16048a utilize a system of ordered slots to sequence multiple power supplies. to determine the sequence order, assign each en_out_ to a slot ranging from slot 0 to slot 11. en_out_(s) assigned to slot 0 are turned on first, followed by out- puts assigned to slot 1, and so on through slot 11. multiple en_out_s assigned to the same slot turn on at the same time. each slot has a built-in configurable sequence delay (registers r50h to r54h) ranging from 20s to 2.4s. during a reverse sequence, slots are turned off in reverse order starting from slot 11. the max16046a/ max16048a may be configured to power-down in simultaneous mode or in reverse sequence mode as set in r54h[4]. see tables 10, 11, and 12 for the en_out_ slot assignment bits and tables 13 and 14 for the sequence delays. monitoring inputs while sequencing an enabled mon_ input may be assigned to a slot rang- ing from slot 1 to slot 12. monitoring inputs are always checked at the beginning of a slot. the inputs are given the power-up fault delay within which they must satisfy the programmed undervoltage limit; otherwise a fault condition will occur. the fault occurs regardless of the critical fault enable bits. this undervoltage limit cannot be disabled during power-up and power-down. en_out_s configured for open-drain, push-pull, or charge-pump operation are always asserted at the end of a slot, following the sequence delay. see tables 10, 11, and 12 for the mon_ slot assignment bits. slot 0 does not monitor any mon_ input. instead, slot 0 waits for the software enable bit r4dh[0] to be a logic 0 and for the voltage on en to rise above 0.525v before asserting any assigned outputs. outputs assigned to slot 0 are asserted before the slot 0 sequence delay. generally, slot 0 controls the enable inputs of power supplies that are first in the sequence. similarly, slot 12 does not control any en_out_ outputs. rather, slot 12 monitors assigned mon_ inputs and then enters the power-on state. generally, slot 12 monitors the last power supplies in the sequence. the power-up sequence is complete when any mon_ inputs assigned to slot 12 exceed their undervoltage thresholds and the sequence delay is expired. if no mon_ inputs are assigned to slot 12, the power-up sequence is complete after the slot sequence delay is expired. the output rail(s) of a power supply should be monitored by one or more mon_ inputs placed in the succeeding slot, ensuring that the output of the supply is not checked until it has first been turned on. for example, if a power supply uses en_out1 located in slot 3 and has two monitoring inputs, mon1 and mon2, they must both be assigned to slot 4. in this example, en_out1 turns on at the end of slot 3. at the start of slot 4, mon1 and mon2 must exceed the undervoltage threshold before the pro- grammed power-up fault delay; otherwise a fault triggers. max16046a fig03 20ms/div v cc 2v/div en_out_ 2v/div 0v reset 2v/div 0v 0v figure 3. reset and en_out_ during power-up, en_out_ is in open-drain active-low configuration max16046a fig04 10ms/div v cc 2v/div en_out_ 2v/div 0v reset 2v/div 0v 0v high-z asserted low uvlo figure 4. reset and en_out_ during power-up, en_out_ is in push-pull active-high configuration
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 31 reset deassertion after any mon_ inputs assigned to slot 12 exceed their undervoltage thresholds, the reset timeouts begin. when the reset timeout completes, reset deasserts. the reset timeout period is set in r19h[6:4] (see table 27). power-down power-down starts when en is pulled low or the software enable bit is set to 1. reset asserts as soon as power-down begins regardless of the reset output dependencies. power down en_out_s simultaneously or in reverse sequence mode by setting the reverse sequence bit (r54h[4]) appropriately. in reverse sequence mode (r54h[4] set to 1), the en_out_s assigned to slot 11 deassert, the max16046a/ max16048a wait for the slot 11 sequence delay and then proceed to slot 10, and so on until the en_out_s assigned to slot 0 turn off. when simultaneous power- down is selected (r54h[4] set to 0), all en_out_s turn off at the same time. table 10. mon_ and en_out_ slot assignment registers register/ eeprom address bit range description [3:0] mon1 slot assignment register 56h [7:4] mon2 slot assignment register [3:0] mon3 slot assignment register 57h [7:4] mon4 slot assignment register [3:0] mon5 slot assignment register 58h [7:4] mon6 slot assignment register [3:0] mon7 slot assignment register 59h [7:4] mon8 slot assignment register [3:0] mon9 slot assignment register* 5ah [7:4] mon10 slot assignment register* [3:0] mon11 slot assignment register* 5bh [7:4] mon12 slot assignment register* [3:0] en_out1 slot assignment register 5eh [7:4] en_out2 slot assignment register [3:0] en_out3 slot assignment register 5fh [7:4] en_out4 slot assignment register [3:0] en_out5 slot assignment register 60h [7:4] en_out6 slot assignment register [3:0] en_out7 slot assignment register 61h [7:4] en_out8 slot assignment register [3:0] en_out9 slot assignment register* 62h [7:4] en_out10 slot assignment register* [3:0] en_out11 slot assignment register* 63h [7:4] en_out12 slot assignment register * * max16046a only
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 32 ______________________________________________________________________________________ table 11. mon_ slot assignment configuration bits description 0000 mon_ is not assigned to a slot 0001 mon_ is assigned to slot 1 0010 mon_ is assigned to slot 2 0011 mon_ is assigned to slot 3 0100 mon_ is assigned to slot 4 0101 mon_ is assigned to slot 5 0110 mon_ is assigned to slot 6 0111 mon_ is assigned to slot 7 1000 mon_ is assigned to slot 8 1001 mon_ is assigned to slot 9 1010 mon_ is assigned to slot 10 1011 mon_ is assigned to slot 11 1100 mon_ is assigned to slot 12 1101 not used 1110 not used 1111 not used table 12. en_out_ slot assignment configuration bits description 0000 en_out_ is not assigned to a slot 0001 en_out_ is assigned to slot 0 0010 en_out_ is assigned to slot 1 0011 en_out_ is assigned to slot 2 0100 en_out_ is assigned to slot 3 0101 en_out_ is assigned to slot 4 0110 en_out_ is assigned to slot 5 0111 en_out_ is assigned to slot 6 1000 en_out_ is assigned to slot 7 1001 en_out_ is assigned to slot 8 1010 en_out_ is assigned to slot 9 1011 en_out_ is assigned to slot 10 1100 en_out_ is assigned to slot 11 1101 not used 1110 not used 1111 not used
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 33 table 13. sequence delays and fault recovery register/ eeprom address bit range description [1:0] power-up fault timeout 00 = 37.5ms 01 = 75ms 10 = 150ms 11 = 300ms [3:2] power-down fault timeout 00 = 37.5ms 01 = 75ms 10 = 150ms 11 = 300ms [4] ins1 pulldown resistor enable 0 = pulldown resistor for ins1 is disabled 1 = pulldown resistor for ins1 is enabled [5] ins2 pulldown resistor enable 0 = pulldown resistor for ins2 is disabled 1 = pulldown resistor for ins2 is enabled [6] ins3 pulldown resistor enable 0 = pulldown resistor for ins3 is disabled 1 = pulldown resistor for ins3 is enabled 4eh [7] ins4 pulldown resistor enable 0 = pulldown resistor for ins4 is disabled 1 = pulldown resistor for ins4 is enabled [2:0] autoretry timeout 000 = 20s 001 = 18.75ms 010 = 37.5ms 011 = 75ms 100 = 150ms 101 = 300ms 110 = 600ms 111 = 2.4s [3] fault recovery mode 0 = autoretry procedure is performed following a fault event 1 = latch-off on fault [5:4] slew rate 00 = 800v/s 01 = 400v/s 10 = 200v/s 11 = 100v/s 4fh [7:6] fault deglitch 00 = 2 conversions 01 = 4 conversions 10 = 8 conversions 11 = 16 conversions
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 34 ______________________________________________________________________________________ table 13. sequence delays and fault recovery (continued) register/ eeprom address bit range description [2:0] slot 0 sequence delay [5:3] slot 1 sequence delay 50h [7:6] slot 2 sequence delay (lsbs) [0] slot 2 sequence delay (msb)see r50h[7:6] [3:1] slot 3 sequence delay [6:4] slot 4 sequence delay 51h [7] slot 5 sequence delay (lsb)see r52h[1:0] [1:0] slot 5 sequence delay [4:2] slot 6 sequence delay 52h [7:5] slot 7 sequence delay [2:0] slot 8 sequence delay [5:3] slot 9 sequence delay 53h [7:6] slot 10 sequence delay (lsbs) [0] slot 10 sequence delay (msb)see r53h[7:6] [3:1] slot 11 sequence delay [4] reverse sequence 0 = power down all en_out_s at the same time (simultaneously) 1 = controlled power-down will be reverse of power-up sequence 54h [7:5] not used table 14. slot sequence delay selection configuration bits slot sequence delay 000 20s 001 18.75ms 010 37.5ms 011 75ms 100 150ms 101 300ms 110 600ms 111 2.4s
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 35 closed-loop tracking the max16046a/max16048a track up to four voltages during any time slot except slot 0 and slot 12. configure gpio1Cgpio4 as sense line inputs (ins_) to monitor tracking voltages. configure gpio6 as faultpu to indicate tracking faults, if desired. see the general-purpose inputs/outputs section for information on configuring gpios. for closed-loop tracking, use mon1, en_out1, and ins1 together to form a complete channel. use mon2, en_out2, and ins2 to form a second complete chan- nel. use mon3, en_out3, and ins3 together to form a third channel. use mon4, en_out4, and ins4 to form a fourth channel. when configured for closed-loop tracking, assign each en_out_ to the same slot as its associated single monitoring input (mon_). for example, if en_out2 is assigned to slot 3, the monitoring input is mon2 and must be assigned to slot 3. this is because the mon_ input, checked at the start of the slot, must be valid before tracking can begin. tracking begins immediate- ly and must finish before the power-up fault timeout expires, or a fault will trigger. en_out_ configured for closed-loop tracking cannot be assigned to slot 0. the tracking control circuitry includes a ramp generator and a comparator control block for each tracked volt- age (see the functional diagram and figure 5). the comparator control block compares each ins_ voltage with a control voltage ramp. if ins_ voltages vary from the control ramp by more than 150mv (typ), the com- parator control block signals an alert that dynamically stops the ramp until the slow ins_ voltage rises to with- in the allowed voltage window. the total tracking time is extended under these conditions, but must still com- plete within the selected power-up/power-down fault timeout. the power-up/power-down tracking fault time- out period is adjustable through r4eh[3:0]. a voltage difference between any two tracking ins_ voltages exceeding 330mv generates a tracking fault, forcing all en_out_ voltages low and generating a fault log. if configured as faultpu , gpio6 asserts when a tracking fault occurs. the comparator control blocks also monitor ins_ voltages with respect to input (mon_) voltages. under normal con- ditions each ins_ tracks the control ramp until the ins_ voltages reach the configured power-good (pg) thresh- olds, set as a programmable percentage of the mon_ voltage. use register r64h to set the pg thresholds (table 15). once pg is detected, the external n-channel fet sat- urates with 5v (typ) applied between gate and source. the slew rate for the control ramp is programmable from 100v/s to 800v/s in r4fh[5:4] (see table 13). power-down initiates when en is forced low or when the software enable bit in r4dh[0] is set to 1. if the reverse sequence bit is set (r54h[4]) ins_ voltages fol- low a falling reference ramp to ground as long as mon_ voltages remain high enough to supply the required voltage/current. if a monitored voltage drops faster than the control ramp voltage or the correspond- ing mon_ voltage falls too quickly, power-down track- ing operation is terminated and all en_out_ voltages are immediately forced to ground. if the reverse sequence bit is set to 0, all en_out_ voltages are forced low simultaneously. the max16046a/max16048a include selectable internal 100 ? pulldown resistors to ensure that tracked voltages are not held high by large external capacitors during a fault event. the pulldowns help to ensure that monitored ins_ voltages are fully discharged before the next power- up cycle is initiated. these pulldowns are high imped- ance during normal operation. set r4eh[7:4] to 1 to enable the pulldown resistors (table 13). these pulldown resistors may also be used with en_out1Cen_out4 channels not configured for closed-loop tracking, which is useful to discharge the output capacitors of a dc-dc converter during shutdown. for this case, configure the gpio as an ins_ input and set the 100 ? pulldown bit, but do not enable closed-loop tracking. connect the ins_ input to the output of the power supply. mon_ en_out_ ins_ v in v out reference ramp logic adc mux v th_pg 100 ? gate drive figure 5. closed-loop tracking
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 36 ______________________________________________________________________________________ dac outputs the max16046a/max16048a feature an 8-bit dac with 12 outputs (max16046a) or 8 outputs (max16048a) for voltage margining. program the voltage on the dac outputs (dacout1Cdacout12) to trim external power-supply voltages, by connecting through a series resistor to the feedback node or to the trim input. dac outputs are high impedance during power-up to pre- vent improper operation of the external power supplies and must be explicitly enabled by setting the appropri- ate dacout_ enable bits. each dacout output has three voltage ranges: 0.4v to 0.8v, 0.6v to 1.2v, and 0.8v to 1.6v. configure dac outputs using registers r12h to r14h (see table 16). calculate dacout_ voltages, v dacout_ , using the fol- lowing equation: v dacout_ = dac acc (v) + ((dac n - 80h) x (dac rng )/255) (v) where dac acc is the dac center code absolute accu- racy and dac rng is the dac output voltage range as listed in the electrical characteristics table and 07h < dac n < f8h. set any dacout_ range configuration register to 00h to switch off the dacout buffer. set the dacout_ enable bit to 0 to leave the dac output as high imped- ance. see table 16 for the registers associated with the dac output ranges. the dac enable bits are not copied from eeprom dur- ing the boot phase; therefore each dacout_ output must be enabled in the r1ch and r1dh registers, locat- ed in the extended page, following power-up. see table 17 for the dac enable bits. to control the voltage on a particular dac output, write the 8-bit binary value to the appropriate output regis- ter; see table 18 for the register locations. although these registers are located in the default page, they are not stored in nonvolatile eeprom and are set to 0 after a por. table 15. power-good (pg) thresholds register/ eeprom address bit range description [1:0] 00 = pg is asserted when monitored v mon1 is 95% of v ins1 01 = pg is asserted when monitored v mon1 is 92.5% of v ins1 10 = pg is asserted when monitored v mon1 is 90% of v ins1 11 = pg is asserted when monitored v mon1 is 87.5% of v ins1 [3:2] 00 = pg is asserted when monitored v mon2 is 95% of v ins2 01 = pg is asserted when monitored v mon2 is 92.5% of v ins2 10 = pg is asserted when monitored v mon2 is 90% of v ins2 11 = pg is asserted when monitored v mon2 is 87.5% of v ins2 [5:4] 00 = pg is asserted when monitored v mon3 is 95% of v ins3 01 = pg is asserted when monitored v mon3 is 92.5% of v ins3 10 = pg is asserted when monitored v mon3 is 90% of v ins3 11 = pg is asserted when monitored v mon3 is 87.5% of v ins3 64h [7:6] 00 = pg is asserted when monitored v mon4 is 95% of v ins4 01 = pg is asserted when monitored v mon4 is 92.5% of v ins4 10 = pg is asserted when monitored v mon4 is 90% of v ins4 11 = pg is asserted when monitored v mon4 is 87.5% of v ins4
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 37 table 16. dacout ranges register/ eeprom address bit range description [1:0] dacout1 range selection: 00 = dacout1 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) [3:2] dacout2 range selection: 00 = dacout2 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) [5:4] dacout3 range selection: 00 = dacout3 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) 12h [7:6] dacout4 range selection: 00 = dacout4 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) [1:0] dacout5 range selection: 00 = dacout5 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) [3:2] dacout6 range selection: 00 = dacout6 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) [5:4] dacout7 range selection: 00 = dacout7 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) 13h [7:6] dacout8 range selection: 00 = dacout8 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max)
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 38 ______________________________________________________________________________________ table 16. dacout ranges (continued) register/ eeprom address bit range description [1:0] dacout9 range selection*: 00 = dacout9 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) [3:2] dacout10 range selection*: 00 = dacout10 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) [5:4] dacout11 range selection*: 00 = dacout11 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) 14h [7:6] dacout12 range selection*: 00 = dacout12 is off 01 = 0.4v (min) to 0.8v (max) 10 = 0.6v (min) to 1.2v (max) 11 = 0.8v (min) to 1.6v (max) table 17. dacout enables extended page address dacout enables [0] 1 = dacout1 is enabled [1] 1 = dacout2 is enabled [2] 1 = dacout3 is enabled [3] 1 = dacout4 is enabled [4] 1 = dacout5 is enabled [5] 1 = dacout6 is enabled [6] 1 = dacout7 is enabled 1ch [7] 1 = dacout8 is enabled [0] 1 = dacout9 is enabled* [1] 1 = dacout10 is enabled* [2] 1 = dacout11 is enabled* [3] 1 = dacout12 is enabled* 1dh [7:4] reserved table 18. dacout voltages register address bit range description 00h [7:0] dacout1 data 01h [7:0] dacout2 data 02h [7:0] dacout3 data 03h [7:0] dacout4 data 04h [7:0] dacout5 data 05h [7:0] dacout6 data 06h [7:0] dacout7 data 07h [7:0] dacout8 data 08h [7:0] dacout9 data* 09h [7:0] dacout10 data* 0ah [7:0] dacout11 data* 0bh [7:0] dacout12 data* * max16046a only * max16046a only * max16046a only
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 39 voltage margining margining is commonly performed while a system is under development, but margining can also be per- formed during the manufacturing process. the supply voltages of external dc-dc regulators can be adjusted by trimming the regulators reference input (for voltage- regulator modules), altering the voltage regulators feedback node, or adjusting a brick power supplys trim input. see the applications information section for sample circuits. margining can be controlled over the serial interface or by using gpio2 and gpio3. before adjusting the voltages using the dac outputs, enable voltage margining func- tionality by setting the margin bit at r4dh[1] to 1 (see table 1) or configure gpio6 as margin (see tables 4 and 5). set dacout_ voltages to the appropriate values and then enable the appropriate dac outputs. to control margining with external circuitry, configure gpio2 and gpio3 as marginup and margindn inputs, respectively. pull marginup low and pull margindn high to select dacout_ voltage values set in registers r66h to r71h. pull margindn low and pull marginup high to select dacout_ values set in registers r72h to r7dh (see tables 19 and 20). pull both marginup and margindn high or low to select dacout_ values set in registers r00h to r0bh. see table 16 for more information on setting the volt- age ranges for the dacout_ outputs. table 20 shows which register values are used for the dac outputs for each state of marginup and margindn . table 20. dacout margining output dependencies marginup (gpio2) margindn (gpio3) dacout register used dacout switch state 1 1 dacout registers r00h to r0bh depends on r1ch, r1dh 1 0 margin dn registers r72h to r7dh closed 0 1 margin up registers r66h to r71h closed 0 0 dacout registers r00h to r0bh depends on r1ch, r1dh table 19. dacout1?acout12 margin data register/ eeprom address bit range description 66h [7:0] dacout1 margin-up data 67h [7:0] dacout2 margin-up data 68h [7:0] dacout3 margin-up data 69h [7:0] dacout4 margin-up data 6ah [7:0] dacout5 margin-up data 6bh [7:0] dacout6 margin-up data 6ch [7:0] dacout7 margin-up data 6dh [7:0] dacout8 margin-up data 6eh [7:0] dacout9 margin-up data* 6fh [7:0] dacout10 margin-up data* 70h [7:0] dacout11 margin-up data* 71h [7:0] dacout12 margin-up data* register/ eeprom address bit range description 72h [7:0] dacout1 margin-down data 73h [7:0] dacout2 margin-down data 74h [7:0] dacout3 margin-down data 75h [7:0] dacout4 margin-down data 76h [7:0] dacout5 margin-down data 77h [7:0] dacout6 margin-down data 78h [7:0] dacout7 margin-down data 79h [7:0] dacout8 margin-down data 7ah [7:0] dacout9 margin-down data* 7bh [7:0] dacout10 margin-down data* 7ch [7:0] dacout11 margin-down data* 7dh [7:0] dacout12 margin-down data* * max16046a only
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 40 ______________________________________________________________________________________ faults the max16046a/max16048a monitor the input (mon_) channels and compare the results with an overvoltage threshold, an undervoltage threshold, and a selectable overvoltage or undervoltage early warning threshold. based on these conditions, the max16046a/ max16048a can assert various fault outputs and save specific information about the channel conditions and voltages into the nonvolatile eeprom. once a critical fault event occurs, the failing channel condition, adc conversions at the time of the fault, or both may be saved by configuring the event logger. the event log- ger records a single failure in the internal eeprom and sets a lock bit which protects the stored fault data from accidental erasure on a subsequent power-up. the max16046a/max16048a are capable of measur- ing overvoltage and undervoltage fault events. fault conditions are detected at the end of each adc con- version. an overvoltage event occurs when the voltage at a monitored input exceeds the overvoltage threshold for that input. an undervoltage fault occurs when the voltage at a monitored input falls below the undervolt- age threshold. fault thresholds are set in registers r23h to r46h as shown in table 21. disabled inputs are not monitored for fault conditions and are skipped over by the input multiplexer. only the upper 8 bits of a conver- sion result are compared with the programmed fault thresholds. inputs not assigned to a sequencing slot are not monitored for fault conditions but are still recorded in the adc results registers. the general-purpose inputs/outputs (gpio1Cgpio6) can be configured as any_fault outputs or dedicated fault1 and fault2 outputs to indicate fault condi- tions. these fault outputs are not masked by the critical fault enable bits shown in table 23. see the general- purpose inputs/outputs section for more information on configuring gpios as fault outputs. table 21. fault thresholds register/ eeprom address description 23h mon1 early warning threshold 24h mon1 overvoltage threshold 25h mon1 undervoltage threshold 26h mon2 early warning threshold 27h mon2 overvoltage threshold 28h mon2 undervoltage threshold 29h mon3 early warning threshold 2ah mon3 overvoltage threshold 2bh mon3 undervoltage threshold 2ch mon4 early warning threshold 2dh mon4 overvoltage threshold 2eh mon4 undervoltage threshold 2fh mon5 early warning threshold 30h mon5 overvoltage threshold 31h mon5 undervoltage threshold 32h mon6 early warning threshold 33h mon6 overvoltage threshold 34h mon6 undervoltage threshold register/ eeprom address description 35h mon7 early warning threshold 36h mon7 overvoltage threshold 37h mon7 undervoltage threshold 38h mon8 early warning threshold 39h mon8 overvoltage threshold 3ah mon8 undervoltage threshold 3bh mon9 early warning threshold* 3ch mon9 overvoltage threshold* 3dh mon9 undervoltage threshold* 3eh mon10 early warning threshold* 3fh mon10 overvoltage threshold* 40h mon10 undervoltage threshold* 41h mon11 early warning threshold* 42h mon11 overvoltage threshold* 43h mon11 undervoltage threshold* 44h mon12 early warning threshold* 45h mon12 overvoltage threshold* 46h mon12 undervoltage threshold* * max16046a only
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 41 deglitch fault conditions are detected at the end of each con- version. if the voltage on an input falls outside a moni- tored threshold for one acquisition, the input multiplexer remains on that channel and performs several succes- sive conversions. to trigger a fault, the input must stay outside the threshold for a certain number of acquisi- tions as determined by the deglitch setting in r4fh[7:6] (see table 25). fault flags fault flags indicate the fault status of a particular input. the fault flag of any monitored input in the device can be read at any time from registers r18h and r19h in the extended page, as shown in table 22. clear a fault flag by writing a 1 to the appropriate bit in the flag register. unlike the fault signals sent to the fault outputs, these bits are masked by the critical fault enable bits (see table 23). the fault flag will only be set if the matching enable bit in the critical fault enable register is also set. critical faults if a specific input threshold is critical to the operation of the system, an automatic fault log can be configured to shut down all the en_out_s and trigger a transfer of fault information to eeprom. for a fault condition to trigger a critical fault, set the appropriate enable bit in registers r48h to r4ch (see table 23). logged fault information is stored in eeprom registers r00h to r0eh (see table 24). once a fault log event occurs, the eeprom is locked and must be unlocked to enable a new fault log to be stored. write a 1 to r5dh[1] to unlock the eeprom. fault information can be configured to store adc conversion results and/or fault flags in registers r01h and r02h. select the critical fault configuration in r47h[1:0]. set r47h[1:0] to 11 to turn off the fault logger. all stored adc results are 8 bits wide. * max16046a only table 22. fault flags extended page address bit range description [0] 1 = mon1 conversion exceeds overvoltage or undervoltage thresholds [1] 1 = mon2 conversion exceeds overvoltage or undervoltage thresholds [2] 1 = mon3 conversion exceeds overvoltage or undervoltage thresholds [3] 1 = mon4 conversion exceeds overvoltage or undervoltage thresholds [4] 1 = mon5 conversion exceeds overvoltage or undervoltage thresholds [5] 1 = mon6 conversion exceeds overvoltage or undervoltage thresholds [6] 1 = mon7 conversion exceeds overvoltage or undervoltage thresholds 18h [7] 1 = mon8 conversion exceeds overvoltage or undervoltage thresholds [0] 1 = mon9 conversion exceeds overvoltage or undervoltage thresholds* [1] 1 = mon10 conversion exceeds overvoltage or undervoltage thresholds* [2] 1 = mon11 conversion exceeds overvoltage or undervoltage thresholds* [3] 1 = mon12 conversion exceeds overvoltage or undervoltage thresholds* 19h [7:4] not used
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 42 ______________________________________________________________________________________ table 23. critical fault configuration and enable bits register/ eeprom address bit range description [1:0] critical fault log control 00 = failed lines and adc conversion values save to eeprom upon critical fault 01 = failed line flags only saved to eeprom upon critical fault 10 = adc conversion values only saved to eeprom upon critical fault 11 = no information saved upon critical fault 47h [7:2] not used [0] 1 = fault log triggered when mon1 is below its undervoltage threshold [1] 1 = fault log triggered when mon2 is below its undervoltage threshold [2] 1 = fault log triggered when mon3 is below its undervoltage threshold [3] 1 = fault log triggered when mon4 is below its undervoltage threshold [4] 1 = fault log triggered when mon5 is below its undervoltage threshold [5] 1 = fault log triggered when mon6 is below its undervoltage threshold [6] 1 = fault log triggered when mon6 is below its undervoltage threshold 48h [7] 1 = fault log triggered when mon8 is below its undervoltage threshold [0] 1 = fault log triggered when mon9 is below its undervoltage threshold* [1] 1 = fault log triggered when mon10 is below its undervoltage threshold* [2] 1 = fault log triggered when mon11 is below its undervoltage threshold* [3] 1 = fault log triggered when mon12 is below its undervoltage threshold* [4] 1 = fault log triggered when mon1 is above its overvoltage threshold [5] 1 = fault log triggered when mon2 is above its overvoltage threshold [6] 1 = fault log triggered when mon3 is above its overvoltage threshold 49h [7] 1 = fault log triggered when mon3 is above its overvoltage threshold [0] 1 = fault log triggered when mon5 is above its overvoltage threshold [1] 1 = fault log triggered when mon6 is above its overvoltage threshold [2] 1 = fault log triggered when mon7 is above its overvoltage threshold [3] 1 = fault log triggered when mon8 is above its overvoltage threshold [4] 1 = fault log triggered when mon9 is above its overvoltage threshold* [5] 1 = fault log triggered when mon10 is above its overvoltage threshold* [6] 1 = fault log triggered when mon11 is above its overvoltage threshold* 4ah [7] 1 = fault log triggered when mon12 is above its overvoltage threshold* [0] 1 = fault log triggered when mon1 is above/below its early earning threshold [1] 1 = fault log triggered when mon2 is above/below its early warning threshold [2] 1 = fault log triggered when mon3 is above/below its early warning threshold [3] 1 = fault log triggered when mon4 is above/below its early warning threshold [4] 1 = fault log triggered when mon5 is above/below its early warning threshold [5] 1 = fault log triggered when mon6 is above/below its early warning threshold [6] 1 = fault log triggered when mon7 is above/below its early warning threshold 4bh [7] 1 = fault log triggered when mon8 is above/below its early warning threshold
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 43 * max16046a only table 23. critical fault configuration and enable bits (continued) register/ eeprom address bit range description [0] 1 = fault log triggered when mon9 is above/below its early warning threshold* [1] 1 = fault log triggered when mon10 is above/below its early warning threshold* [2] 1 = fault log triggered when mon11 is above/below its early warning threshold* [3] 1 = fault log triggered when mon12 is above/below its early warning threshold* 4ch [7:4] not used * max16046a only table 24. fault log eeprom eeprom address bit range description [3:0] power-up/power-down fault register slot where p ower-u p / p ower-down fault is detected [4] tracking fault bits if 0, trackin g fault occurred on mon1/en_out1/ins1 [5] if 0, tracking fault occurred on mon2/en_out2/ins2 [6] if 0, tracking fault occurred on mon3/en_out3/ins3 00h [7] if 0, tracking fault occurred on mon4/en_out4/ins4 [0] if 1, fault occurred on mon1 [1] if 1, fault occurred on mon2 [2] if 1, fault occurred on mon3 [3] if 1, fault occurred on mon4 [4] if 1, fault occurred on mon5 [5] if 1, fault occurred on mon6 [6] if 1, fault occurred on mon7 01h [7] if 1, fault occurred on mon8 [0] if 1, fault occurred on mon9* [1] if 1, fault occurred on mon10* [2] if 1, fault occurred on mon11* [3] if 1, fault occurred on mon12* 02h [7:4] not used 03h [7:0] mon_ adc fault information (only the 8 msbs of converted channels are saved following a fault event) mon1 conversion result at the time the fault lo g was tri gg ered 04h [7:0] mon2 conversion result at the time the fault log was triggered 05h [7:0] mon3 conversion result at the time the fault log was triggered 06h [7:0] mon4 conversion result at the time the fault log was triggered 07h [7:0] mon5 conversion result at the time the fault log was triggered 08h [7:0] mon6 conversion result at the time the fault log was triggered 09h [7:0] mon7 conversion result at the time the fault log was triggered 0ah [7:0] mon8 conversion result at the time the fault log was triggered 0bh [7:0] mon9 conversion result at the time the fault log was triggered* 0ch [7:0] mon10 conversion result at the time the fault log was triggered* 0dh [7:0] mon11 conversion result at the time the fault log was triggered* 0eh [7:0] mon12 conversion result at the time the fault log was triggered*
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 44 ______________________________________________________________________________________ power-up/power-down faults all en_outs are deasserted if an overvoltage or under- voltage fault is detected during power-up/power-down (regardless of the critical fault enable bits). under these conditions, information of the failing slot is stored in eeprom r00h[3:0] unless r47h[1:0] is set to 11 (see table 23). if there is a tracking fault on a channel configured for closed-loop tracking, a fault log operation occurs and the bits representing the failed tracking channels are set to 0 unless r47h[1:0] is set to 11 (see table 24). autoretry/latch mode for critical faults, the max16046a/max16048a can be configured for one of two fault management methods: autoretry or latch-on-fault. set r4fh[3] to 0 to select autoretry mode. in this configuration, the device will shut down after a critical fault event and then restart fol- lowing a configurable delay. use r4fh[2:0] to select an autoretry delay from 20s to 2.4s. see table 25 for more information on setting the autoretry delay. set r4fh[3] to 1 to select the latch-on-fault mode. in this configuration en_out_s are deasserted after a critical fault event. the device does not re-initiate the power-up sequence until en is toggled or the software enable bit is reset to 0. see the enable section for more information on setting the software enable bit. if fault information is stored in eeprom (see the critical faults section) and autoretry mode is selected, set an autoretry delay greater than the time required for the storing operation. if fault information is stored in eeprom and latch-on-fault mode is chosen, toggle en or reset the software enable bit only after the comple- tion of the storing operation. if saving information about the failed lines only, ensure a delay of at least 90ms before the restart procedure. otherwise, ensure a mini- mum 306ms timeout. this ensures that adc conver- sions are completed and values are stored correctly in eeprom. see table 26 for more information about required fault log operation periods. table 25. fault recovery configuration register/ eeprom address bit range description [2:0] autoretry delay 000 = 20s 001 = 18.75ms 010 = 37.5ms 011 = 75ms 100 = 150ms 101 = 300ms 110 = 600ms 111 = 2.4s [3] fault recovery mode 0 = autoretry procedure is performed following a fault event 1 = latchoff on fault [5:4] slew rate 00 = 800v/s 01 = 400v/s 10 = 200v/s 11 = 100v/s 4fh [7:6] fault deglitch 00 = 2 conversions 01 = 4 conversions 10 = 8 conversions 11 = 16 conversions
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 45 reset the reset output, reset , is asserted during power- up/power-down and deasserts following the reset time- out period once the power-up sequence is complete. the power-up sequence is complete when any mon_ inputs assigned to slot 12 exceed their undervoltage thresholds. if no mon_ inputs are assigned to slot 12, the power-up sequence is complete after the slot sequence delay is expired. reset is a configurable output that monitors selected mon_ voltages during normal operation. reset also depends on any monitoring input that has one or more critical fault enable bits set. use r19h[1:0] to configure reset to assert on an overvoltage fault, undervoltage fault, or both. use r19h[3:2] to configure reset as an active-high/active-low push-pull/open-drain output. if desired, configure gpio4 as a manual reset input, mr , and pull mr low to assert reset . reset includes a programmable timeout. see table 27 for reset depen- dencies and configuration registers. table 26. eeprom fault log operation period fault control register r47h[1:0] description minimum required shutdown period (ms) 00 failed lines and adc values saved 306 01 failed lines saved 90 10 adc values saved 252 11 no information saved n/a table 27. reset configuration and dependencies register/ eeprom address bit range description [1:0] reset output configuration 00 = reset is asserted if at least one of the selected inputs exceeds its undervoltage threshold 01 = reset is asserted if at least one of the selected inputs exceeds its early warning threshold 10 = reset is asserted if at least one of the selected inputs exceeds its overvoltage threshold 11 = reset is asserted if any of the selected inputs exceeds undervoltage or overvoltage thresholds [2] 0 = reset is an active-low output 1 = reset is an active-high output [3] 0 = reset is an open-drain output 1 = reset is a push-pull output [6:4] reset timeout 000 = 25s 001 = 3ms 010 = 37.5ms 011 = 150ms 100 = 300ms 101 = 600ms 110 = 1200ms 111 = 2400ms 19h [7] reserved
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 46 ______________________________________________________________________________________ watchdog timer the watchdog timer can operate together with or inde- pendently of the max16046a/max16048a. when oper- ating in dependent mode, the watchdog is not activated until the sequencing is complete and reset is de-asserted. when operating in independent mode, the watchdog timer is independent of the sequencing operation and activates immediately after v cc exceeds the uvlo threshold and the boot phase is complete. set r4dh[3] to 0 to configure the watchdog in depen- dent mode. set r4dh[3] to 1 to configure the watchdog in independent mode. see table 28 for more informa- tion on configuring the watchdog timer in dependent or independent mode. dependent watchdog timer operation the watchdog timer can be used to monitor p activity in two modes. flexible timeout architecture provides an adjustable watchdog startup delay of up to 192s, allow- ing complicated systems to complete lengthy boot-up routines. an adjustable watchdog timeout allows the supervisor to provide quick alerts when processor activity fails. after each reset event (v cc drops below uvlo then returns above uvlo, software reboot, man- ual reset ( mr ), en input going low then high, or watch- dog reset) and once sequencing is complete, the watchdog startup delay provides an extended time for the system to power up and fully initialize all p and system components before assuming responsibility for routine watchdog updates. set r55h[6] to 1 to enable the watchdog startup delay. set r55h[6] to 0 to disable the watchdog startup delay. the normal watchdog timeout period, t wdi , begins after the first transition on wdi before the conclusion of the long startup watchdog period, t wdi_startup (figures 6 and 7). during the normal operating mode, wdo asserts if the p does not toggle wdi with a valid transi- tion (high-to-low or low-to-high) within the standard timeout period, t wdi . wdo remains asserted until wdi is toggled or reset is asserted (figure 7). while en is low, or r55h[7] is a 0, the watchdog timer is in reset. the watchdog timer does not begin counting until the power-on mode is reached and reset is deasserted. the watchdog timer is reset and wdo deasserts any time reset is asserted (figure 8). the watchdog timer will be held in reset while reset is asserted. the watchdog can be configured to control the reset output as well as the wdo output. reset is pulsed low for the reset timeout, t rp , when the watchdog timer expires and the watchdog reset output enable bit (r55h[7]) is set to 1. therefore, wdo pulses low for a short time (approximately 1s) when the watchdog timer expires. reset is not affected by the watchdog timer when the watchdog reset output enable bit (r55h[7]) is set to 0. see table 29 for more information on configuring watchdog functionality. * max16046a only table 27. reset configuration and dependencies (continued) register/ eeprom address bit range description [0] reset dependencies 1 = reset is dependent on mon1 [1] 1 = reset is dependent on mon2 [2] 1 = reset is dependent on mon3 [3] 1 = reset is dependent on mon4 [4] 1 = reset is dependent on mon5 [5] 1 = reset is dependent on mon6 [6] 1 = reset is dependent on mon7 1ah [7] 1 = reset is dependent on mon8 [0] 1 = reset is dependent on mon9* [1] 1 = reset is dependent on mon10* [2] 1 = reset is dependent on mon11* [3] 1 = reset is dependent on mon12* 1bh [7:4] reserved
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 47 last mon_ wdi v th t wdi_startup < t wdi t rp reset < t wdi figure 6. normal watchdog startup sequence wdi wdo 0v v cc 0v v cc < t wdi < t wdi < t wdi < t wdi t wdi < t wdi < t wdi t wdi figure 7. watchdog timer operation wdi wdo 0v 0v v cc v cc 0v v cc < t wdi 1 figure 8. watchdog startup sequence with watchdog reset output enable bit (r55h[7]) set to 1
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 48 ______________________________________________________________________________________ table 28. watchdog mode selection register/ eeprom address bit range description 0 software enable bit 0 = enabled. en must also be high to begin sequencing. 1 = disabled (factory default) 1 margin bit 1 = margin functionality is enabled 0 = margin disabled 2 early warning selection bit 0 = early warning thresholds are undervoltage thresholds 1 = early warning thresholds are overvoltage thresholds 3 watchdog mode selection bit 0 = watchdog timer is in dependent mode 1 = watchdog timer is in independent mode 4dh [7:4] not used table 29. watchdog enables and configuration register/ eeprom address bit range description [2:0] watchdog timeout 000 = 1.5ms 001 = 6ms 010 = 18.75ms 011 = 75ms 100 = 300ms 101 = 1200ms 110 = 2400ms 111 = 4800ms [4:3] watchdog startup delay 00 = 38.4s 01 = 76.8s 10 = 153.6s 11 = 192s [5] watchdog enable 1 = watchdog enabled 0 = watchdog disabled [6] watchdog startup delay enable 1 = watchdog startup delay enabled 0 = watchdog startup delay disabled 55h [7] watchdog r eset output enable 1 = watchdog timeout asserts reset output 0 = watchdog timeout does not assert reset output
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 49 independent watchdog timer operation when r4dh[3] is 1 the watchdog timer operates in the independent mode. in the independent mode, the watchdog timer operates as if it were a separate chip. the watchdog timer is activated immediately upon v cc exceeding uvlo and once the boot-up sequence is finished. if reset is asserted by the sequencer state machine, the watchdog timer and wdo will not be affected. there will be a long startup delay if r55h[6] is a 1. if r55h[6] is a 0, there will not be a long startup delay. in independent mode, if the watchdog reset output enable bit r55h[7] is set to 1, when the watchdog timer expires, wdo will be asserted, then reset will be asserted. wdo will then be deasserted. wdo will be low for 3 system clock cycles or approximately 1s. if the watchdog reset output enable bit (r55h[7]) is set to 0, when the wdt expires, wdo will be asserted but reset will not be affected. miscellaneous table 30 lists several miscellaneous programmable items. register r5ch provides storage space for a user- defined configuration or firmware version number. bit r5dh[0] locks and unlocks the configuration registers. bit r5dh[1] locks and unlocks eeprom addresses 00h to 11h. write data to eeprom r5dh as normally done; however, to toggle a bit in register r5dh, write a 1 to that bit. the r65h[2:0] bits contain a read-only manufac- turing revision code. table 30. miscellaneous settings register/ eeprom address bit range description 5ch [7:0] user identification. eight bits of memory for user-defined identification. [0] configuration lock 0 = configuration registers and eeprom writable. 1 = configuration registers and eeprom [except r5dh] locked. [1] eeprom fault data lock flag (set automatically after fault log is triggered): 0 = eeprom is not locked. a triggered fault log stores fault information to eeprom. 1 = eeprom addresses 00h to 11h are locked. write a 1 to this bit to toggle the flag. 5dh [7:2] not used [2:0] manufacturing revision code. this register is read only. not stored in eeprom. 65h [7:3] not used
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 50 ______________________________________________________________________________________ i 2 c/smbus-compatible serial interface the max16046a/max16048a feature an i 2 c/smbus- compatible 2-wire serial interface consisting of a serial data line (sda) and a serial clock line (scl). sda and scl facilitate bidirectional communication between the max16046a/max16048a and the master device at clock rates up to 400khz. figure 1 shows the 2-wire interface timing diagram. the max16046a/max16048a are transmit/receive slave-only devices, relying upon a master device to generate a clock signal. the master device (typically a microcontroller) initiates a data transfer on the bus and generates scl to permit that transfer. a master device communicates to the max16046a/ max16048a by transmitting the proper address followed by command and/or data words. the slave address input, a0, is capable of detecting four different states, allowing multiple identical devices to share the same seri- al bus. the slave address is described further in the slave address section. each transmit sequence is framed by a start (s) or repeated start (sr) condition and a stop (p) condition. each word transmitted over the bus is 8 bits long and is always followed by an acknowledge pulse. scl is a logic input, while sda is an open-drain input/output. scl and sda both require external pullup resistors to generate the logic-high voltage. use 4.7k ? for most applications. bit transfer each clock pulse transfers one data bit. the data on sda must remain stable while scl is high (figure 9); otherwise the max16046a/max16048a registers a start or stop condition (figure 10) from the master. sda and scl idle high when the bus is not busy. start and stop conditions both scl and sda idle high when the bus is not busy. a master device signals the beginning of a transmis- sion with a start condition by transitioning sda from high to low while scl is high. the master device issues a stop condition by transitioning sda from low to high while scl is high. a stop condition frees the bus for another transmission. the bus remains active if a repeated start condition is generated, such as in the block read protocol (see figure 1). early stop conditions the max16046a/max16048a recognize a stop condi- tion at any point during transmission except if a stop condition occurs in the same high pulse as a start condition. this condition is not a legal i 2 c format; at least one clock pulse must separate any start and stop condition. repeated start conditions a repeated start may be sent instead of a stop condition to maintain control of the bus during a read operation. the start and repeated start condi- tions are functionally identical. data line stable, data valid sda scl change of data allowed figure 9. bit transfer p s start condition sda scl stop condition figure 10. start and stop conditions
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 51 acknowledge the acknowledge bit (ack) is the 9th bit attached to any 8-bit data word. the receiving device always gen- erates an ack. the max16046a/max16048a generate an ack when receiving an address or data by pulling sda low during the 9th clock period (figure 11). when transmitting data, such as when the master device reads data back from the max16046a/max16048a, the device waits for the master device to generate an ack. monitoring ack allows for detection of unsuccessful data transfers. an unsuccessful data transfer occurs if the receiving device is busy or if a system fault has occurred. in the event of an unsuccessful data transfer, the bus master should reattempt communication at a later time. the max16046a/max16048a generate a nack after the command byte received during a soft- ware reboot, while writing to the eeprom, or when receiving an illegal memory address. slave address use the slave address input, a0, to allow multiple identi- cal devices to share the same serial bus. connect a0 to gnd, dbp (or an external supply voltage greater than 2v), scl, or sda to set the device address on the bus. see table 31 for a listing of all possible 7-bit addresses. scl 1 s 2 89 sda by transmitter sda by receiver clock pulse for acknowledge nack ack figure 11. acknowledge table 31. setting the i 2 c/smbus slave address a0 slave address 0 1010 00xr 1 1010 01xr scl 1010 10xr sda 1010 11xr x = dont care, r = read/write select bit
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 52 ______________________________________________________________________________________ send byte the send byte protocol allows the master device to send one byte of data to the slave device (see figure 12). the send byte presets a register pointer address for a subsequent read or write. the slave sends a nack instead of an ack if the master tries to send a memory address or command code that is not allowed. if the master sends 94h or 95h, the data is ack, because this could be the start of the write block or read block. if the master sends a stop condition before the slave asserts an ack, the internal address pointer does not change. if the master sends 96h, this signifies a software reboot. the send byte procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address or com- mand code. 5) the addressed slave asserts an ack (or nack) on sda. 6) the master sends a stop condition. receive byte the receive byte protocol allows the master device to read the register content of the max16046a/ max16048a (see figure 12). the eeprom or register address must be preset with a send byte or write word protocol first. once the read is complete, the internal pointer increases by one. repeating the receive byte protocol reads the contents of the next address. the receive byte procedure follows: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a read bit (high). 3) the addressed slave asserts an ack on sda. 4) the slave sends 8 data bits. 5) the master asserts a nack on sda. 6) the master generates a stop condition. write byte the write byte protocol (see figure 12) allows the mas- ter device to write a single byte in the default page, extended page, or eeprom page, depending on which page is currently selected. the write byte proce- dure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address. 5) the addressed slave asserts an ack on sda. 6) the master sends an 8-bit data byte. 7) the addressed slave asserts an ack on sda. 8) the master sends a stop condition. to write a single byte, only the 8-bit memory address and a single 8-bit data byte are sent. the data byte is written to the addressed location if the memory address is valid. the slave will assert a nack at step 5 if the memory address is not valid. read byte the read byte protocol (see figure 12) allows the mas- ter device to read a single byte located in the default page, extended page, or eeprom page depending on which page is currently selected. the read byte proce- dure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends an 8-bit memory address. 5) the addressed slave asserts an ack on sda. 6) the master sends a repeated start condition. 7) the master sends the 7-bit slave address and a read bit (high). 8) the addressed slave asserts an ack on sda. 9) the slave sends an 8-bit data byte. 10) the master asserts a nack on sda. 11) the master sends a stop condition. if the memory address is not valid, it is nacked by the slave at step 5 and the address pointer is not modified.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 53 command codes the max16046a/max16048a use eight command codes for block read, block write, and other com- mands. see table 32 for a list of command codes. to initiate a software reboot, send 96h using the send byte format. a software-initiated reboot is functionally the same as a hardware-initiated power-on reset. during boot-up, eeprom configuration data in the range of 0fh to 7dh is copied to the same register addresses in the default page. send command code 97h to trigger a fault store to eeprom. configure the critical fault log control register (r47h) to store adc conversion results and/or fault flags in registers once the command code has been sent. using command code 98h allows access to the extend- ed page, which contains registers for adc conversion results, dacout enables, and gpio input/output data. use command code 99h to return to the default page. send command code 9ah to access the eeprom page. once command code 9ah has been sent, all addresses are recognized as eeprom addresses only. send command code 9bh to return to the default page. block write the block write protocol (see figure 12) allows the master device to write a block of data (1 byte to 16 bytes) to memory. the destination address should be preloaded by a previous send byte command; other- wise the block write command begins to write at the current address pointer. after the last byte is written, the address pointer remains preset to the next valid address. if the number of bytes to be written causes the address pointer to exceed ffh for eeprom or 7dh for configuration registers, the address pointer stays at ffh or 7dh, overwriting this memory address with the remaining bytes of data. the last data byte sent is stored at register address ffh. the slave generates a nack at step 5 if the command code is invalid or if the device is busy, and the address pointer is not altered. the block write procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends the 8-bit command code for block write (94h). 5) the addressed slave asserts an ack on sda. 6) the master sends the 8-bit byte count (1 byte to 16 bytes), n . 7) the addressed slave asserts an ack on sda. 8) the master sends 8 bits of data. 9) the addressed slave asserts an ack on sda. 10) repeat steps 8 and 9 n - 1 times. 11) the master sends a stop condition. block read the block read protocol (see figure 12) allows the master device to read a block of up to 16 bytes from memory. read fewer than 16 bytes of data by issuing an early stop condition from the master or by generat- ing a nack with the master. the destination address should be preloaded by a previous send byte com- mand; otherwise the block read command begins to read at the current address pointer. if the number of bytes to be read causes the address pointer to exceed ffh for the configuration register or eeprom, the address pointer stays at ffh and the last data byte read is from register rffh. the block read procedure is the following: 1) the master sends a start condition. 2) the master sends the 7-bit slave address and a write bit (low). 3) the addressed slave asserts an ack on sda. 4) the master sends 8 bits of the block read com- mand (95h). 5) the slave asserts an ack on sda, unless busy. 6) the master generates a repeated start condition. 7) the master sends the 7-bit slave address and a read bit (high). table 32. command codes command code action 94h write block 95h read block 96h reboot eeprom in register file 97h trigger fault store to eeprom 98h extended page access on 99h extended page access off 9ah eeprom page access on 9bh eeprom page access off
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 54 ______________________________________________________________________________________ 8) the slave asserts an ack on sda. 9) the slave sends the 8-bit byte count (16). 10) the master asserts an ack on sda. 11) the slave sends 8 bits of data. 12) the master asserts an ack on sda. 13) repeat steps 11 and 12 up to fifteen times. 14) the master asserts a nack on sda. 15) the master sends a stop condition. read byte format s slave address slave address ack command ack sr ack data byte nack p 7 bits 8 bits 7 bits 8 bits command byte: prepares device for following read. data byte: data comes from the register set by the command byte. 01 block write format s address ack command ack byte count= n ack data byte 1 ack data byte ... ack data byte n ack p 7 bits 8 bits 8 bits 8 bits 8 bits command byte: destination address data byte: data goes into the register set by the command 8 bits 0 block read format s address ack command ack sr address ack byte count= n ack ack ack nack p 7 bits 8 bits 7 bits 8 bits 8 bits 8 bits 8 bits command byte: prepares device for block operation. data byte: data is read from the register (or eeprom location) set by the command code 0 1 slave to master master to slave s address 7 bits send byte format wr ack data 8 bits ack p data byte: presets the internal address pointer or represents a command. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. slave address: equivalent to chip- select line of a 3-wire interface. data byte: presets the internal address pointer or represents a command. slave address: equivalent to chip- select line of a 3-wire interface. 0 write byte format s address ack command ack data ack p 7 bits 8 bits 8 bits command byte: selects register or eeprom location you are writing to. data byte: data goes into the register (or eeprom location) set by the command byte. 0 s = start condition p = stop condition sr = repeated start condition d.c. = don't care ack = acknowledge, sda pulled low during rising edge of scl nack = not acknowlege, sda left high during rising edge of scl all data is clocked in/out of the device on rising edges of scl = sda transistions from high to low during period of scl = sda transistions from low to high during period of scl s address 7 bits receive byte format wr wr wr wr wr wr wr ack data 8 bits nack p 1 data byte 1 data byte ... data byte n figure 12. i 2 c/smbus protocols
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 55 jtag serial interface the max16046a/max16048a contain a jtag port that complies with a subset of the ieee 1149.1 specifi- cation. either the i 2 c or the jtag interface may be used to access internal memory; however, only one interface is allowed to run at a time. the max16046a/ max16048a do not support ieee 1149.1 boundary- scan functionality. the max16046a/max16048a con- tain extra jtag instructions and registers not included in the jtag specification that provide access to inter- nal memory. the extra instructions include load address, write data, read data, reboot, save, and usercode. test access port (tap) controller instruction register [length = 5 bits] bypass register [length = 1 bit] identification register [length = 32 bits] user code register [length = 32 bits] memory address register [length = 8 bits] memory read register [length = 8 bits] memory write register [length = 8 bits] 11111 00000 00011 00100 00101 00110 00111 mux 2 tdo tdi tms tck 01000 registers and eeprom 01001 01010 01011 01100 mux 1 00111 01000 01001 01010 01011 01100 reboot save setextram seteepadd rstextram rsteepadd command decoder r pu v db figure 13. jtag block diagram
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 56 ______________________________________________________________________________________ test access port (tap) controller state machine the tap controller is a finite state machine that responds to the logic level at tms on the rising edge of tck. see figure 14 for a diagram of the finite state machine. the possible states are described below: test-logic-reset: at power-up, the tap controller is in the test-logic-reset state. the instruction register con- tains the idcode instruction. all system logic of the device operates normally. this state can be reached from any state by driving tms high for five clock cycles. run-test/idle: the run-test/idle state is used between scan operations or during specific tests. the instruction register and test data registers remain idle. select-dr-scan: all test data registers retain their pre- vious state. with tms low, a rising edge of tck moves the controller into the capture-dr state and initiates a scan sequence. tms high during a rising edge on tck moves the controller to the select-ir-scan state. capture-dr: data can be parallel-loaded into the test data registers selected by the current instruction. if the instruction does not call for a parallel load or the select- ed test data register does not allow parallel loads, the test data register remains at its current value. on the rising edge of tck, the controller goes to the shift-dr state if tms is low or it goes to the exit1-dr state if tms is high. test-logic-reset 1 1 11 0 0 run-test/idle 0 0 0 0 1 1 1 0 0 1 0 1 1 0 1 0 1 select-dr-scan select-ir-scan capture-dr capture-ir shift-dr shift-ir exit1-dr exit1-ir pause-dr pause-ir exit2-dr exit2-ir update-dr update-ir 0 0 0 0 1 1 0 1 1 figure 14. tap controller state diagram
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 57 shift-dr: the test data register selected by the current instruction connects between tdi and tdo and shifts data one stage toward its serial output on each rising edge of tck while tms is low. on the rising edge of tck, the controller goes to the exit1-dr state if tms is high. exit1-dr: while in this state, a rising edge on tck puts the controller in the update-dr state. a rising edge on tck with tms low puts the controller in the pause-dr state. pause-dr: shifting of the test data registers halts while in this state. all test data registers retain their previous state. the controller remains in this state while tms is low. a rising edge on tck with tms high puts the con- troller in the exit2-dr state. exit2-dr: a rising edge on tck with tms high while in this state puts the controller in the update-dr state. a rising edge on tck with tms low enters the shift-dr state. update-dr: a falling edge on tck while in the update- dr state latches the data from the shift register path of the test data registers into a set of output latches. this prevents changes at the parallel output because of changes in the shift register. on the rising edge of tck, the controller goes to the run-test/idle state if tms is low or goes to the select-dr-scan state if tms is high. select-ir-scan: all test data registers retain their previ- ous states. the instruction register remains unchanged during this state. with tms low, a rising edge on tck moves the controller into the capture-ir state. tms high during a rising edge on tck puts the controller back into the test-logic-reset state. capture-ir: use the capture-ir state to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of tck. if tms is high on the rising edge of tck, the controller enters the exit1-ir state. if tms is low on the rising edge of tck, the controller enters the shift-ir state. shift-ir: in this state, the shift register in the instruction register connects between tdi and tdo and shifts data one stage for every rising edge of tck toward the tdo serial output while tms is low. the parallel outputs of the instruction register as well as all test data regis- ters remain at their previous states. a rising edge on tck with tms high moves the controller to the exit1-ir state. a rising edge on tck with tms low keeps the controller in the shift-ir state while moving data one stage through the instruction shift register. exit1-ir: a rising edge on tck with tms low puts the controller in the pause-ir state. if tms is high on the rising edge of tck, the controller enters the update-ir state. pause-ir: shifting of the instruction shift register halts temporarily. with tms high, a rising edge on tck puts the controller in the exit2-ir state. the controller remains in the pause-ir state if tms is low during a ris- ing edge on tck. exit2-ir: a rising edge on tck with tms high puts the controller in the update-ir state. the controller loops back to shift-ir if tms is low during a rising edge of tck in this state. update-ir: the instruction code that has been shifted into the instruction shift register latches to the parallel outputs of the instruction register on the falling edge of tck as the controller enters this state. once latched, this instruction becomes the current instruction. a rising edge on tck with tms low puts the controller in the run-test/idle state. with tms high, the controller enters the select-dr-scan state. instruction register the instruction register contains a shift register as well as a latched parallel output and is 5 bits in length. when the tap controller enters the shift-ir state, the instruc- tion shift register connects between tdi and tdo. while in the shift-ir state, a rising edge on tck with tms low shifts the data one stage toward the serial output at tdo. a rising edge on tck in the exit1-ir state or the exit2-ir state with tms high moves the controller to the update-ir state. the falling edge of that same tck latches the data in the instruction shift register to the instruction register parallel output. instructions support- ed by the max16046a/max16048a and the respective operational binary codes are shown in table 33.
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 58 ______________________________________________________________________________________ usercode: when the usercode instruction latches into the parallel instruction register, the user-code data register is selected. the device user-code loads into the user-code data register on the rising edge of tck following entry into the capture-dr state. shift-dr can be used to shift the user-code out serially through tdo. see table 35. this instruction may be used to help identify multiple max16046a/max16048a devices con- nected in a jtag chain. bypass: when the bypass instruction is latched into the instruction register, tdi connects to tdo through the 1-bit bypass test data register. this allows data to pass from tdi to tdo without affecting the devices normal operation. idcode: when the idcode instruction is latched into the parallel instruction register, the identification data register is selected. the device identification code is loaded into the identification data register on the rising edge of tck following entry into the capture-dr state. shift-dr can be used to shift the identification code out serially through tdo. during test-logic-reset, the idcode instruction is forced into the instruction regis- ter. the identification code always has a 1 in the lsb position. the next 11 bits identify the manufacturers jedec number and number of continuation bytes fol- lowed by 16 bits for the device and 4 bits for the ver- sion. see table 34. table 33. jtag instruction set table 34. 32-bit identification code instruction hex code selected register/action bypass 1fh bypass. mandatory instruction code. idcode 00h manufacturer id code and part number usercode 03h user code (user-defined id) load address 04h load address register content read data 05h memory read write data 06h memory write reboot 07h resets the device save 08h stores current fault information in eeprom setextram 09h extended page access on rstextram 0ah extended page access off seteepadd 0bh eeprom page access on rsteepadd 0ch eeprom page access off msb lsb version (4 bits) device id (16 bits) manufacturer id (11 bits) fixed value (1 bit) 0000 0000000000000001 00011001011 1 table 35. 32-bit user-code data msb lsb d.c. (dont cares) i 2 c/smbus slave address user identification (firmware version) 00000000000000000 see table 31 r5ch[7:0] contents
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 59 load address: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the max16046a/max16048a. when the load address instruction latches into the instruction register, tdi connects to tdo through the 8-bit memory address test data register during the shift-dr state. read data: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the max16046a/max16048a. when the read data instruction latches into the instruction register, tdi con- nects to tdo through the 8-bit memory read test data register during the shift-dr state. write data: this is an extension to the standard ieee 1149.1 instruction set to support access to the memory in the max16046a/max16048a. when the write data instruction latches into the instruction reg- ister, tdi connects to tdo through the 8-bit memory write test data register during the shift-dr state. reboot: this is an extension to the standard ieee 1149.1 instruction set to initiate a software controlled reset to the max16046a/max16048a. when the reboot instruction latches into the instruction register, the max16046a/max16048a resets and immediately begins the boot-up sequence. save: this is an extension to the standard ieee 1149.1 instruction set that triggers a fault log. the current adc conversion results along with fault information are saved to eeprom depending on the configuration of the critical fault log control register (r47h). setextram: this is an extension to the standard ieee 1149.1 instruction set that allows access to the extended page. extended registers include adc conversion results, dacout enables, and gpio input/output data. rstextram: this is an extension to the standard ieee 1149.1 instruction set. use rstextram to return to the default page and disable access to the extended page. seteepadd: this is an extension to the standard ieee 1149.1 instruction set that allows access to the eeprom page. once the seteepadd command has been sent, all addresses are recognized as eeprom addresses only. user eeprom (r9ch to rffh) cannot be accessed from the jtag interface. use the smbus interface to access user eeprom. rsteepadd: this is an extension to the standard ieee 1149.1 instruction set. use rsteepadd to return to the default page and disable access to the eeprom. applications information unprogrammed device behavior when the eeprom has not been programmed using the jtag or i 2 c interface, the default configuration of the en_out_ outputs is open-drain active-low. if it is necessary to hold an en_out_ high or low to prevent premature startup of a power supply before the eeprom is programmed, connect a resistor to ground or the supply voltage. avoid connecting a resistor to ground if the output is to be configured as open-drain with a separate pullup resistor. device behavior at power-up when v cc is ramped from 0v, the reset output is high impedance until v cc reaches 1.4v, at which point it is driven low. all other outputs are high impedance until v cc reaches 2.85v, when the eeprom contents are copied into register memory, and after which the out- puts assume their programmed states. if en is driven by external logic instead of from the center tap of a v cc - connected resistive divider, ensure that an active-high pulse occurs on en within 1.5ms of v cc exceeding 2.85v. if the external driving logic is in the high-imped- ance state during power-up, this pulse can be created by connecting an external pullup resistor to en. margining power supplies the max16046a/max16048a can margin or shift the voltages on external power supplies to facilitate proto- typing or manufacturing tests. there are several differ- ent ways to margin power supplies: one method feeds a current into the feedback node of a dc-dc converter or ldo, and another method feeds a current into the trim input on a dc-dc module. feedback method see figure 15 for the connections of the max16046a/ max16048a to a power supply using the feedback node method. the output voltage, v out , can be calcu- lated using the following formula: where v ref is the internal reference voltage of the power supply and v dacout_ is the output voltage of the max16046a/max16048a dacout_ output. select r 1 and r 2 to obtain the desired output voltage with no trim in effect (v dacout_ = v ref ). set the dac range bits such that v ref falls approximately halfway within the dacout_ output range (see the dac outputs section). the resistor r 3 varies the amount of control that the dacout_ voltage has on the output voltage of the power supply. large values of r 3 corre- spond to a higher degree of resolution control over the output voltage, and small values of r 3 correspond to a lesser degree of resolution control. vv1 r r r r r r v out ref 1 3 1 2 1 3 dacout_ =++ ? ? ? ? ? ? ? ? ?
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 60 ______________________________________________________________________________________ filtering the dac outputs some applications require filtering of the dac outputs. this is especially necessary in applications that require a large distance between the power supplies to be margined and the max16046a/max16048a, or those that require immunity to noise. a simple rc filter may be inserted (see figure 16). the calculations change slightly for this configuration. for dc margining calculations, r 3 = r 3a + r 3b . to cal- culate the lowpass cutoff frequency, use the following formula: place resistor r 3a and the capacitor, c, as close as possible to the feedback node. trim input method to connect the max16046a/max16048a to a power supply using the trim input method, see figure 17. calculate the output voltage, v out , as follows: where v ref is the reference voltage of the power sup- ply; r 1 , r 2 , r 3 , and r 4 are resistors internal to the power supply; r 5 is an optional series resistor connect- ing the trim input to the dacout_ output; and v dacout_ is the output voltage of the dacout_ output. calculate the ratio of r 1 and r 2 using the following for- mula: resistors r 3 and r 4 and the reference voltage, v ref , may be derived from the formulas given in the dc-dc converter data sheet where trim input functionality is discussed. dc-dc module data sheets usually include trim-up and trim-down formulas in the following form: where ? is the fraction of the total correction. another form of trim-up and trim-down formulas may appear as follows: trim down:r k r k 100 % rk adj_down 3 4 ? ? ? ? () = () () ? + + () () ? ? ? ? ? ? () = rk trim up:r k v 3 adj_up out_no ? ? m m3 ref r k 100 % v% ?? ? () + () () ? ? ? ? ? ? ? ? ? rk 3 ? ???? ? () + () + () () ? ? ? ? ? ? ? ? 100 rk rk % % 43 trim down:r k 1 rk r adj_down 3 4 ? ? ? ? () = ? ? ? ? ? ? () ? ? k k trim up:r k v v 1 adj_up out_nom ref ? ? () () = ? ? ? ? ? ? ? ? ? ? ? ? ? ? () () ? ? 1 rk rk 34 ? ? ?? 1 r r v v 1 2 out_nom ref + ? ? ? ? ? ? = v1 r r rv (r r)v rr out 1 2 3 dacout_ 4 5 ref 3 =+ ? ? ? ? ? ? ++ + 4 45 r + ? ? ? ? ? ? f 1 2r c 3b = max16046a max16048a fb v ref v dacout_ r 2 r 3 r 1 out dc-dc or ldo figure 15. connections for margining using feedback method max16046a max16048a fb c v ref v dacout_ r 2 r 3a r 3b r 1 out dc-dc or ldo figure 16. dacout filter
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 61 set the dacout_ range bits (see the dac outputs section) such that v ref falls approximately halfway within the dacout range. set r 5 to vary the amount of control the dac has on the output voltage of the power supply. large values of r 5 correspond to higher degree of resolution control over the output voltage, and small values of r 5 correspond to lesser degree of resolution control. be sure to respect the minimum and maximum output voltages that the dc-dc converter is capable of generating. the following is an example that illustrates the use of the formulas for calculating the margin up and margin down values. this example uses a generic 3.3v dc-dc converter with a trim input. below are the margin up and margin down formulas taken from the data sheet for the power supply: by inspecting these formulas, v ref = 1.225v, r 3 = 1k ? , and r 4 = 1k ? . set the dacout_ range from 0.8v to 1.6v to fit the reference voltage. the output voltage of the dc-dc converter is 3.3v; therefore the ratio (1 + r 1 /r 2 ) = v out /v ref = 3.3/1.225 = 2.69. set r 5 to zero to use the widest trim range possible (increase r 5 to decrease the trim range). insert these values into the equations for the output voltage: for v dacout_ = 0.8v, v out = 2.72v, and for v dacout_ = 1.6v, v out = 3.80v. these output volt- ages correspond with a margin down limit of -17.6% and a margin up limit of 15.2%. since the reference voltage is not exactly in the center of the dacout_ range, the margin limits are not symmetrical. to decrease the margin limits, increase the value of r 5 . maintaining power during a fault condition power to the max16046a/max16048a must be main- tained for a specific period of time to ensure a success- ful eeprom fault log operation during a fault that removes power to the circuit. the amount of time required depends on the settings in the fault control register (r47h[1:0]) according to table 36. maintain power for shutdown during fault conditions in applications where the always-on power supply cannot be relied upon by placing a diode and a large capaci- tor between the voltage source, v in , and v cc (figure 18). the capacitor value depends on v in and the time delay required, t fault_save . use the following formula to calculate the capacitor size: where the capacitance is in farads and t fault_save is in seconds. i cc(max) is 6.5ma, v diode is the voltage drop across the diode, and v uvlo is 2.85v. for exam- ple, with a v in of 14v, a diode drop of 0.7v, and a t fault_save of 0.306s, the minimum required capaci- tance is 190f. c ti vv v fault_save cc(max) in diode uvlo = ? ? v2.69 1k v 1k 1.225 2k 2 out dacout = () + ? ? ? ? ? ? = ?? ? . .69 v 1.225 2 dacout_ () + () trim down:r 100 % 2k trim u adj_down = ? ? ? ? ? ? () ? ? ? p p:r v (100 %) 1.225 % 100 2 adj_up out_nom = + + ? ? ? ? ? ? ? % k % ? ? ? ? ? ? () max16046a max16048a trim v ref v dacout_ r 2 r 5 r 1 out dc-dc or ldo r 4 r 3 figure 17. connections for margining using trim input method table 36. eeprom fault log operation period fault control register value r47h[1:0] description required period t fault_save (ms) 00 failed lines and adc values saved 306 01 failed lines saved 90 10 adc values saved 252 11 no information saved
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 62 ______________________________________________________________________________________ driving high-side mosfet switches the max16046a/max16048a use external n-channel mosfet switches for voltage tracking applications. to configure the part for closed-loop voltage tracking using series-pass mosfets, configure up to four of the programmable outputs (en_out1Cen_out4) of the max16046a/max16048a as closed-loop tracking out- puts and configure up to four of the gpios as sense- return inputs (ins1Cins4). connect the en_out_ output to the gate of an n-channel mosfet, connect the source of the mosfet to the ins_ feedback input, and monitor the drain side of the mosfet with the cor- responding mon_ input (see figure 19). both the input and the output must be assigned to the same slot (see the closedCloop tracking section). configure the power-up and power-down slew rates in the configura- tion registers. to provide additional control over power- down, enable the internal 100 ? pulldown resistors on the ins_ connections. up to six of the programmable outputs (en_out1C en_out6) of the max16046a/max16048a may be con- figured as charge-pump outputs. in this case, they can drive the gates of series-pass n-channel mosfets with- out closed-loop tracking functionality. when configured in this way, these outputs act as simple power switches to turn on the voltage supply rails. approximate the slew rate, sr, using the following formula: where i cp is the 6a (typ) charge-pump source cur- rent, c gate is the gate capacitance of the mosfet, and c ext is the capacitance connected from the gate to ground. power-down is not well controlled due to the absence of the 100 ? pulldowns. if more than six series-pass mosfets are required for an application, additional series-pass p-channel mosfets may be connected to outputs configured as active-low open drain (figure 20). connect a pullup resistor from the gate to the source of the mosfet and ensure the absolute maximum ratings of the max16046a/max16048a are not exceeded. sr i cc cp gate ext = + () max16046a max16048a v cc c v in gnd figure 18. power circuit for shutdown during fault conditions mon_ en_out_ ins_ v in v out reference ramp logic adc mux v th_pg 100 ? gate drive figure 19. closed-loop tracking max16046a max16048a v out r mon_ en_out_ v in figure 20. connection for a p-channel series-pass mosfet
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 63 simple slew-rate control is accomplished by adding a capacitor from the gate to ground. the slew rate is approximated by the rc charge curve of the pullup resistor acting with the capacitor from gate to ground. note that the power-off is not well controlled due to the absence of the 100 ? pulldowns. ensure that mosfets have a low gate-to-source threshold (v gs_th ) and r ds(on) . see table 37 for rec- ommended n-channel mosfets. layout and bypassing bypass dbp and abp each with a 1f ceramic capacitor to gnd. bypass v cc with a 10f capacitor to ground. avoid routing digital return currents through a sensitive analog area, such as an analog supply input return path or abps bypass capacitor ground connection. use dedi- cated analog and digital ground planes. connect the capacitors as close as possible to the device. table 37. recommended mosfets manufacturer part max v ds (v) v gs _ th (v) r ds(on) at v gs = 4.5v (m ? ) i max at 50mv voltage drop (a) q g (typ) (nc) package fdc633n 30 0.67 42 1.19 11 super sot-6 fdp8030l fdb8030l 30 1.5 4.5 11.11 120 to-220 to-263ab fdd6672a 30 1.2 9.5 5.26 33 to-252 fairchild fds8876 30 2.5 10.2 2.94 15 so-8 si7136dp 20 3 4.5 11.11 24.5 so-8 si4872dy 30 1 10 5 27 so-8 sud50n02-09p 20 3 17 2.94 10.5 to-252 vishay si1488dh 20 0.95 49 1.02 6 sot-363 sc70-6 irl3716 20 3 4.8 10.4 53 to220ab d 2 pak to-262 irl3402 20 0.7 10 5 78 (max) to220ab irl3715z 20 2.1 15.5 3.22 7 to220ab d 2 pak to-262 international rectifier irlm2502 20 1.2 45 1.11 8 sot23-3 micro3
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 64 ______________________________________________________________________________________ register map page address read/write description ext 00h r mon1 adc result register (msb) ext 01h r mon1 adc result register (lsb) ext 02h r mon2 adc result register (msb) ext 03h r mon2 adc result register (lsb) ext 04h r mon3 adc result register (msb) ext 05h r mon3 adc result register (lsb) ext 06h r mon4 adc result register (msb) ext 07h r mon4 adc result register (lsb) ext 08h r mon5 adc result register (msb) ext 09h r mon5 adc result register (lsb) ext 0ah r mon6 adc result register (msb) ext 0bh r mon6 adc result register (lsb) ext 0ch r mon7 adc result register (msb) ext 0dh r mon7 adc result register (lsb) ext 0eh r mon8 adc result register (msb) ext 0fh r mon8 adc result register (lsb) ext 10h r mon9 adc result register (msb)* ext 11h r mon9 adc result register (lsb)* ext 12h r mon10 adc result register (msb)* ext 13h r mon10 adc result register (lsb)* ext 14h r mon11 adc result register (msb)* ext 15h r mon11 adc result register (lsb)* ext 16h r mon12 adc result register (msb)* ext 17h r mon12 adc result register (lsb)* ext 18h r/w fault registerfailed line flags ext 19h r/w fault registerfailed line flags ext 1ah r/w gpio data out ext 1bh r gpio data in ext 1ch r/w dac enables ext 1dh r/w dac enables default 00h r/w dacout1 default 01h r/w dacout2 default 02h r/w dacout3 default 03h r/w dacout4 default 04h r/w dacout5 default 05h r/w dacout6 default 06h r/w dacout7 default 07h r/w dacout8 default 08h r/w dacout9* default 09h r/w dacout10*
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 65 register map (continued) page address read/write description default 0ah r/w dacout11* default 0bh r/w dacout12* eeprom 00h r/w power-up fault registers eeprom 01h r/w failed line flags (fault registers) eeprom 02h r/w failed line flags (fault registers) eeprom 03h r/w mon1 conversion result at time of fault eeprom 04h r/w mon2 conversion result at time of fault eeprom 05h r/w mon3 conversion result at time of fault eeprom 06h r/w mon4 conversion result at time of fault eeprom 07h r/w mon5 conversion result at time of fault eeprom 08h r/w mon6 conversion result at time of fault eeprom 09h r/w mon7 conversion result at time of fault eeprom 0ah r/w mon8 conversion result at time of fault eeprom 0bh r/w mon9 conversion result at time of fault* eeprom 0ch r/w mon10 conversion result at time of fault* eeprom 0dh r/w mon11 conversion result at time of fault* eeprom 0eh r/w mon12 conversion result at time of fault* def/ee 0fh r/w adc mon4Cmon1 voltage ranges def/ee 10h r/w adc mon8Cmon5 voltage ranges def/ee 11h r/w adc mon12Cmon9 voltage ranges* def/ee 12h r/w dacout4Cdacout1 voltage ranges def/ee 13h r/w dacout8Cdacout5 voltage ranges def/ee 14h r/w dacout12Cdacout9 voltage ranges* def/ee 15h r/w fault1 dependencies def/ee 16h r/w fault1 dependencies def/ee 17h r/w fault2 dependencies def/ee 18h r/w fault2 dependencies def/ee 19h r/w reset output configuration def/ee 1ah r/w reset output dependencies def/ee 1bh r/w reset output dependencies def/ee 1ch r/w gpio configuration def/ee 1dh r/w gpio configuration def/ee 1eh r/w gpio configuration def/ee 1fh r/w en_out1Cen_out3 output configuration def/ee 20h r/w en_out3Cen_out6 output configuration def/ee 21h r/w en_out6Cen_out9 output configuration* def/ee 22h r/w en_out10Cen_out12 output configuration* def/ee 23h r/w mon1 early warning threshold def/ee 24h r/w mon1 overvoltage threshold def/ee 25h r/w mon1 undervoltage threshold
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 66 ______________________________________________________________________________________ register map (continued) page address read/write description def/ee 26h r/w mon2 early warning threshold def/ee 27h r/w mon2 overvoltage threshold def/ee 28h r/w mon2 undervoltage threshold def/ee 29h r/w mon3 early warning threshold def/ee 2ah r/w mon3 overvoltage threshold def/ee 2bh r/w mon3 undervoltage threshold def/ee 2ch r/w mon4 early warning threshold def/ee 2dh r/w mon4 overvoltage threshold def/ee 2eh r/w mon4 undervoltage threshold def/ee 2fh r/w mon5 early warning threshold def/ee 30h r/w mon5 overvoltage threshold def/ee 31h r/w mon5 undervoltage threshold def/ee 32h r/w mon6 early warning threshold def/ee 33h r/w mon6 overvoltage threshold def/ee 34h r/w mon6 undervoltage threshold def/ee 35h r/w mon7 early warning threshold def/ee 36h r/w mon7 overvoltage threshold def/ee 37h r/w mon7 undervoltage threshold def/ee 38h r/w mon8 early warning threshold def/ee 39h r/w mon8 overvoltage threshold def/ee 3ah r/w mon8 undervoltage threshold def/ee 3bh r/w mon9 early warning threshold* def/ee 3ch r/w mon9 overvoltage threshold* def/ee 3dh r/w mon9 undervoltage threshold* def/ee 3eh r/w mon10 early warning threshold* def/ee 3fh r/w mon10 overvoltage threshold* def/ee 40h r/w mon10 undervoltage threshold* def/ee 41h r/w mon11 early warning threshold* def/ee 42h r/w mon11 overvoltage threshold* def/ee 43h r/w mon11 undervoltage threshold* def/ee 44h r/w mon12 early warning threshold* def/ee 45h r/w mon12 overvoltage threshold* def/ee 46h r/w mon12 undervoltage threshold* def/ee 47h r/w fault control def/ee 48h r/w faults causing emergency eeprom save def/ee 49h r/w faults causing emergency eeprom save def/ee 4ah r/w faults causing emergency eeprom save def/ee 4bh r/w faults causing emergency eeprom save def/ee 4ch r/w faults causing emergency eeprom save def/ee 4dh r/w software enable /margin
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 67 register map (continued) page address read/write description def/ee 4eh r/w power-up/power-down pulldown resistors def/ee 4fh r/w autoretry, slew rate, and adc fault deglitch def/ee 50h r/w sequence delays def/ee 51h r/w sequence delays def/ee 52h r/w sequence delays def/ee 53h r/w sequence delays def/ee 54h r/w sequence delays/reverse sequence bit def/ee 55h r/w watchdog timer setup def/ee 56h r/w mon2Cmon1 slot assignment from slot 1 to slot 12 def/ee 57h r/w mon4Cmon3 slot assignment from slot 1 to slot 12 def/ee 58h r/w mon6Cmon5 slot assignment from slot 1 to slot 12 def/ee 59h r/w mon8Cmon7 slot assignment from slot 1 to slot 12 def/ee 5ah r/w mon10Cmon9 slot assignment from slot 1 to slot 12* def/ee 5bh r/w mon12Cmon11 slot assignment from slot 1 to slot 12* def/ee 5ch r/w customer firmware version def/ee 5dh r/w eeprom and configuration lock def/ee 5eh r/w en_out2Cen_out1 slot assignment from slot 0 to slot 11 def/ee 5fh r/w en_out4Cen_out2 slot assignment from slot 0 to slot 11 def/ee 60h r/w en_out6Cen_out5 slot assignment from slot 0 to slot 11 def/ee 61h r/w en_out8Cen_out7 slot assignment from slot 0 to slot 11 def/ee 62h r/w en_out10Cen_out9 slot assignment from slot 0 to slot 11* def/ee 63h r/w en_out12Cen_out11 slot assignment from slot 0 to slot 11* def/ee 64h r/w ins power-good (pg) thresholds def/ee 65h r manufacturing revision code def/ee 66h r/w dacout1margin up def/ee 67h r/w dacout2margin up def/ee 68h r/w dacout3margin up def/ee 69h r/w dacout4margin up def/ee 6ah r/w dacout5margin up def/ee 6bh r/w dacout6margin up def/ee 6ch r/w dacout7margin up def/ee 6dh r/w dacout8margin up def/ee 6eh r/w dacout9margin up* def/ee 6fh r/w dacout10margin up* def/ee 70h r/w dacout11margin up* def/ee 71h r/w dacout12margin up* def/ee 72h r/w dacout1margin dn def/ee 73h r/w dacout2margin dn def/ee 74h r/w dacout3margin dn def/ee 75h r/w dacout4margin dn
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 68 ______________________________________________________________________________________ register map (continued) page address read/write description def/ee 76h r/w dacout5margin dn def/ee 77h r/w dacout6margin dn def/ee 78h r/w dacout7margin dn def/ee 79h r/w dacout8margin dn def/ee 7ah r/w dacout9margin dn* def/ee 7bh r/w dacout10margin dn* def/ee 7ch r/w dacout11margin dn* def/ee 7dh r/w dacout12margin dn* def/ee 7ehC93h reserved eeprom 9chCffh r/w user eeprom * max16046a only note: ext refers to registers contained in the extended page, default refers to registers contained in the default page, eeprom refers to eeprom memory locations, and def/ee refers to locations that are stored in eeprom and loaded into the same addresses in the default page on boot-up. chip information process: bicmos package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a +, #, or - in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. land pattern no. 56 tqfn-ep t5688+3 21-0135 90-0047 6 thin sot23 c64e+6 21-0084 90-0328
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers ______________________________________________________________________________________ 69 46 47 48 49 50 43 44 45 51 29 30 31 32 33 34 35 36 37 38 mon11 sda en_out7 tqfn (8mm x 8mm) + top view en_out6 en_out5 en_out4 en_out3 en_out2 en_out1 gpio4 gpio3 scl tdi tms tdo tck gpio6 gnd en gpio5 dacout2 dacout1 dacout4 dacout3 mon10 mon9 mon8 mon7 mon6 a0 reset mon12 mon5 mon4 mon3 mon2 39 mon1 dacout8 dacout9 dacout10 dacout11 dacout12 abp dacout5 ep dacout6 dacout7 v cc dbp gnd gpio1 gpio2 52 en_out8 53 54 55 en_out11 en_out10 en_out9 56 en_out12 20 19 18 17 16 24 23 22 21 15 26 25 28 27 40 41 42 11 10 9 8 7 6 5 4 3 2 14 13 12 1 max16046a 46 47 48 49 50 43 44 45 51 29 30 31 32 33 34 35 36 37 38 n.c. sda en_out7 tqfn (8mm x 8mm) + en_out6 en_out5 en_out4 en_out3 en_out2 en_out1 gpio4 gpio3 scl tdi tms tdo tck gpio6 gnd en gpio5 dacout2 dacout1 dacout4 dacout3 n.c. n.c. mon8 mon7 mon6 a0 reset n.c. mon5 mon4 mon3 mon2 39 mon1 dacout8 n.c. n.c. n.c. n.c. abp dacout5 ep dacout6 dacout7 v cc dbp gnd gpio1 gpio2 52 en_out8 53 54 55 n.c. n.c. n.c. 56 n.c. 20 19 18 17 16 24 23 22 21 15 26 25 28 27 40 41 42 11 10 9 8 7 6 5 4 3 2 14 13 12 1 max16048a pin configurations
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers 70 ______________________________________________________________________________________ 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 mon9 sda en_out12 tqfp (10mm x 10mm) top view en_out11 en_out10 en_out9 en_out8 en_out7 en_out6 en_out5 en_out4 en_out3 52 53 49 50 51 en_out2 en_out1 gpio4 gpio3 n.c. scl tdi tms tdo tck n.c. gnd gpio5 gpio6 dacout1 en dacout3 dacout2 dacout4 gpio2 gpio1 gnd dbp v cc abp dacout12 dacout11 dacout10 dacout9 33 34 35 36 37 dacout8 dacout7 dacout6 dacout5 n.c. mon8 n.c. n.c. mon7 mon6 reset n.c. mon12 mon11 mon10 mon5 mon4 mon3 mon2 48 n.c. mon1 64 n.c. a0 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 max16046a 58 59 60 61 62 54 55 56 57 63 38 39 40 41 42 43 44 45 46 47 n.c. sda n.c. tqfp (10mm x 10mm) top view n.c. n.c. n.c. en_out8 en_out7 en_out6 en_out5 en_out4 en_out3 52 53 49 50 51 en_out2 en_out1 gpio4 gpio3 n.c. scl tdi tms tdo tck n.c. gnd gpio5 gpio6 dacout1 en dacout3 dacout2 dacout4 gpio2 gpio1 gnd dbp v cc abp n.c. n.c. n.c. n.c. 33 34 35 36 37 dacout8 dacout7 dacout6 dacout5 n.c. mon8 n.c. n.c. mon7 mon6 reset n.c. n.c. n.c. n.c. mon5 mon4 mon3 mon2 48 n.c. mon1 64 n.c. a0 23 22 21 20 19 27 26 25 24 18 29 28 32 31 30 17 11 10 9 8 7 6 5 4 3 2 16 15 14 13 12 1 max16048a pin configurations (continued)
max16046a/max16048a 12-channel/8-channel eeprom-programmable system managers with nonvolatile fault registers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 71 ? 2010 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 4/10 initial release 1 9/10 added text to the enable , instruction register , and device behavior at power-up sections, style edits, updated package information 16, 19, 54, 59, 68

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